
Rev. 0.9 / July 2004
5
HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
A1
BA1
Register
Mode Register
Decoder
Decoder
Counter
Row Active
Active
Counter
Data Out Control
CAS Latency
Counter
DQ0
DQ1
DQ30
DQ31
& Timer
Pipe Line Control
Bank Select
CLK
CKE
CS
RAS
CAS
DQM3
x32 Bank 3
Array
Y decoder
1M x32 Bank 0
1M x32 Bank 1
1M x32 Bank 2
1M
X
S
A0
A11
BA0
A
Address
Row
Pre
Column
Pre
Column Add
Column
Burst
Refresh
Self Refresh Logic
I
S
WE
DQM0
DQM1
DQM2
X
X
Cell
Memory
X