參數(shù)資料
型號: HY57V281620ETP-5
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
中文描述: 8M X 16 SYNCHRONOUS DRAM, 4.5 ns, PDSO54
封裝: 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54
文件頁數(shù): 9/13頁
文件大?。?/td> 126K
代理商: HY57V281620ETP-5
Rev. 1.1 / J an. 2005
9
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
DC CHARACTERISTICS II
(T
A
= 0 to 70
o
C
)
Note:
1. I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V281620ET(P) Series:
Normal Power
HY57V281620ELT(P) Series: Low Power
Parameter
Sym-
bol
Test Condition
Speed
Unit Note
5
6
7
H
Operating Current
I
DD1
Burst length=1, One bank active
t
RC
t
RC
(min), I
OL
=0mA
120
110
100
100
mA
1
Precharge Standby Current
in Power Down Mode
I
DD2P
CKE
V
IL
(max), t
CK
= 15ns
2
mA
I
DD2PS
CKE
V
IL
(max), t
CK
=
2
mA
Precharge Standby Current
in Non Power Down Mode
I
DD2N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
=
15ns
Input signals are changed one time dur-
ing 2clks.
All other pins
V
DD
-0.2V or
0.2V
18
mA
I
DD2NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
15
Active Standby Current
in Power Down Mode
I
DD3P
CKE
V
IL
(max), t
CK
= 15ns
3
mA
I
DD3PS
CKE
V
IL
(max), t
CK
=
3
Active Standby Current
in Non Power Down Mode
I
DD3N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
=
15ns
Input signals are changed one time dur-
ing 2clks.
All other pins
V
DD
-0.2V or
0.2V
40
mA
I
DD3NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
35
Burst Mode Operating Cur-
rent
I
DD4
t
CK
t
CK
(min), I
OL
=0mA
All banks active
120
110
100
100
mA
1
Auto Refresh Current
I
DD5
t
RC
t
RC
(min), All banks active
210
200
190
190
mA
2
Self Refresh Current
I
DD6
CKE
0.2V
Normal
2
mA
3
Low power
800
uA
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