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| 型號(hào)： | HY57V281620ET-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 126K |
| 代理商： | HY57V281620ET-H |
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Rev. 1.1 / J an. 2005
10
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note:
1. Assume t
R
/ t
F
(input rise and fall time) is 1ns. If t
R
& t
F
> 1ns, then [(t
R
+t
F
)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If t
R
> 1ns,
then (t
R
/2-0.5)ns should be added to the parameter.
Parameter
Sym-
bol
5
6
7
H
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
System
Clock
Cycle Time
CAS
Latency=3
t
CK3
5.0
1000
6.0
1000
7.0
1000
7.5
1000
ns
CAS
Latency=2
t
CK2
10
10
10
10
ns
Clock High Pulse Width
t
CHW
1.75
-
2.0
-
2.0
-
2.5
-
ns
1
Clock Low Pulse Width
t
CLW
1.75
-
2.0
-
2.0
-
2.5
-
ns
1
Access Time
From Clock
CAS
Latency=3
t
AC3
-
4.5
-
5.4
-
5.4
-
5.4
ns
2
CAS
Latency=2
t
AC2
-
6.0
-
6.0
-
6.0
-
6.0
ns
Data-out Hold Time
t
OH
2.0
-
2.0
-
2.5
-
2.5
-
ns
Data-Input Setup Time
t
DS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Data-Input Hold Time
t
DH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
Address Setup Time
t
AS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Address Hold Time
t
AH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
CKE Setup Time
t
CKS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
CKE Hold Time
t
CKH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
Command Setup Time
t
CS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Command Hold Time
t
CH
0.8
-
0.8
-
0.8
-
0.8
-
ns
1
CLK to Data Output in Low-Z Time
t
OLZ
1.0
-
1.0
-
1.5
-
1.5
-
ns
CLK to
Data Output
in High-Z Time
CAS
Latency=3
t
OHZ3
-
4.5
-
5.4
-
5.4
-
5.4
ns
CAS
Latency=2
t
OHZ2
-
6.0
-
6.0
-
6.0
-
6.0
ns
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| HY57V281620ETP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
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