參數(shù)資料
型號(hào): HW-V5GBE-DK-UNI-G-J
廠商: Xilinx Inc
文件頁(yè)數(shù): 37/91頁(yè)
文件大?。?/td> 0K
描述: KIT DEV GIGABIT ETHERNET VIRTEX5
產(chǎn)品變化通告: Product Notice_Dev Systems Product
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
類型: FPGA
適用于相關(guān)產(chǎn)品: XC5VLX50T-FFG1136
所含物品: 板 - 不包括電源 -
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
42
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.10
0.00
0.11
0.00
0.12
0.00
ns
TISCCK_CE / TISCKC_CE(2)
CE pin Setup/Hold with respect to CLK (for CE1)
0.43
–0.24
0.49
–0.24
0.59
–0.24
ns
TISCCK_CE2 / TISCKC_CE2(2)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
0.03
0.11
0.04
0.13
0.06
0.15
ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.34
–0.12
0.37
–0.12
0.39
–0.12
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
0.31
–0.09
0.33
–0.09
0.36
–0.08
ns
TISDCK_DDR /TISCKD_DDR
D pin Setup/Hold with respect to CLK at DDR mode
0.34
–0.12
0.37
–0.12
0.39
–0.12
ns
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
0.31
–0.09
0.33
–0.09
0.36
–0.08
ns
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
0.46
0.51
0.60
ns
Propagation Delays
TISDO_DO
D input to DO output pin
0.20
0.22
0.26
ns
Notes:
1.
Recorded at 0 tap value.
2.
TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
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