參數(shù)資料
型號(hào)： HV7161SPA2
廠商： Electronic Theatre Controls, Inc.
英文描述： CMOS Image Sensor with Image Signal Processing
中文描述： 的CMOS圖像傳感器和圖像信號(hào)處理
文件頁(yè)數(shù)： 9/72頁(yè)
文件大?。?/td> 2023K
代理商： HV7161SPA2
Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
Output pins
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 9 -
2005 MagnaChip Semiconductor Ltd.
400KHz. With SDA pin, SCK timing should satisfy the standard I2C bus timing.
Y[7:0]
active state, which VSYNC is low and HSYNC is high level. Data output is generated
sequentially whenever VCLK is triggered from low to high level. So, you must capture the
image data whenever VCLK is triggered from high to low level. If HSYNC is got to
inactive state, each Y pin generates high-impedance output - necessary when an imaging
system including sensor uses the common-bus mode. The first image data is normally
BLUE color in the case of Bayer output mode, and LUMINANCE, YCbCr output mode. In
power-down mode, Y[7:0] pins have a state of Hi-Z during HSYNC pin is low level.
C[7:0]
With data bus mode set to RGB 4:4:4-16bit output or YCbCr 4:4:4-
16bit output, video chrominance output is available only when VSYNC and HSYNC is
active state, that VSYNC is low and HSYNC is high level (Otherwise, with 8bit data
output mode, C pin always goes to high-impedance output mode). Data output is
generated sequentially whenever VCLK is triggered from low to high level. So, you must
capture the image data whenever VCLK is triggered from high to low level. If HSYNC is
got to inactive state, each Y pin generates high-impedance output - necessary when an
imaging system including sensor uses the common-bus mode. In power-down mode,
C[7:0] pins have a state of Hi-Z during HSYNC pin is low level.
VCLK
Video clock is always generated while sensor is being active operation.
When HSYNC is active high, video clock has pulse count as a pixel amount
corresponding to 1-line of specific image window. Data output is generated sequentially
whenever VCLK is triggered from low to high level. So, you must capture the image data
whenever VCLK is triggered from high to low level. When VSYNC is low and HSYNC is
high level, total VCLK pulse count is equal to a total pixel amount of specific image
window.
Note :
With OUTINV[0] set to '1', valid data is generated when VCLK is trigged from
high to low level, and you can capture the image data when VCLK is trigged from low to
high level.
HSYNC
Image data is valid, when HSYNC is high
VSYNC
VSYNC is active at start of image data frame.
STROBE
Though sensor has enough integration time to capture
image, sensor can’t obtain good image quality in dark environment. For this situation,
sensor can generate strobe signal for driving external strobe circuit. The strobe output is
active high when integration time is over than core frame time((Video Height Time + 1) X
(Video Width Time + HBLANK)). Because sensor uses progressive exposure method,
strobe signal should cover all line(all pixels).
Note :
If a sensor is got into hard or soft sleep mode, all output pins generate high-
impedance output - necessary when an imaging system including sensor uses the
common-bus mode.
Video luminance output is available only when VSYNC and HSYNC is
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