參數(shù)資料
型號(hào)： HV7161SPA2
廠商： Electronic Theatre Controls, Inc.
英文描述： CMOS Image Sensor with Image Signal Processing
中文描述： 的CMOS圖像傳感器和圖像信號(hào)處理
文件頁(yè)數(shù)： 55/72頁(yè)
文件大?。?/td> 2023K
代理商： HV7161SPA2
Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
PLL Control Mode A [PCTRA : a0h : 01h]
7
6
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 55 -
2005 MagnaChip Semiconductor Ltd.
5
4
3
2
1
0
Reserved
VCO
Power
Down
0
PLL
Power
Down
0
Bypass
Mode
0
0
0
0
0
1
VCO Power Down
(Active High)
When VCO Power Down is active, VCO does not oscillate. For getting out
of VCO Power Down, VCO initialization is required.
PLL Power Down
(Active High)
When PLL Power Down is active, digital circuits of PLL do not operate and
the charge pump circuit is disabled. Also Bypass Mode or Sleep
Mode(SCTRB[4]) register is set to high, PLL goes into sleep.
0
PLL output clock is 1/F(ck).
1
PLL output clock is the same of PLL input clock.
Bypass Mode
* VCO initialization
To ensure the proper operation of the PLL, the activation of VCO initialization signal is required
just after the deactivation of the VCO Power Down. During power-up sequence VCO initialization
signal is recommended for more than 100ns.
PLL Control Mode B [PCTRB : a1h : 1dh]
7
6
5
4
Reserved
Post Divisor
0
0
0
1
The value of Post Divisor according to the output frequency
3
2
1
0
Charge Pump Bias
1
1
1
0
F(ck)
Post Divisor
Min
Max
11
5MHz
12.5MHz
10
10MHz
25MHz
01
20MHz
50MHz
00
40MHz
100MHz
PLL Reference Divisor [PREFDIV : a3h : 01h]
7
6
5
4
3
2
1
0
PLL Reference Divisor
0
0
0
0
0
0
0
1
PLL Feedback Divisor High [PFDDIVH : a4h : 00h]
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