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參數(shù)資料
| 型號： | HV302NG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 電源管理 |
| 英文描述： | Sequencing Hotswap Controllers |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 618K |
| 代理商： | HV302NG |
3 Rev. D 04/17/02
Power Good Outputs
(Referenced to V
EE
pin)
V
PWRGD-x(hi)
Power Good Pin Breakdown Voltage
V
PWRGD-x(lo)
Power Good Pin Output Low Voltage
I
PWRGD-x(lk)
Maximum Leakage Current
Dynamic Characteristics
t
GATEHLOV
OV Comparator Transition
t
GATEHLUV
UV Comparator Transition
Note 1:
This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
Note 2:
This voltage depends on the characteristics of the external N-Channel MOSFET. V
to
= 3V for an IRF530.
*IRF530 is a registered trademark of International Rectifier.
90
V
V
μ
A
PWRGD-x = HI Z
I
PWRGD
= 1mA, PWRGD-x = LOW
V
PWRGD
= 90V, PWRGD-x = HI Z
0.5
<1.0
0.8
10
500
500
ns
ns
Pinout
4
5
6
7
8
9
10
11
1
2
3
12
13
14
PWRGD-D (HV312)
________
PWRGD-D (HV302)
PWRGD-C (HV312)
________
PWRGD-C (HV302)
PWRGD-B (HV312)
________
PWRGD-B (HV302)
PWRGD-A (HV312)
________
PWRGD-A (HV302)
OV
UV
VEE
VDD
TD
TC
TB
RAMP
GATE
SENSE
PWRGD Logic
Model
Condition
PWRGD-A/B/C/D
0
1
1
0
INACTIVE (Not Ready)
ACTIVE (Ready)
INACTIVE (Not Ready)
ACTIVE (Ready)
V
EE
HI Z
HI Z
V
EE
HV302
HV312
Pin Description
PWRGD-D –
This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-C goes active.
PWRGD-C –
This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-B goes active.
PWRGD-B –
This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-A goes active.
PWRGD-A –
This Power Good Output Pin is held inactive on initial
power application and goes active when the external MOSFET is
fully turned on.
OV –
This Over Voltage (OV) sense pin, when raised above its
high threshold will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.
UV
– This Under Voltage (UV) sense pin, when below its low
threshold limit will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin
rises above the high threshold limit, initiating a new start-up cycle.
V
EE
– This pin is the negative terminal of the power supply input to
the circuit.
V
DD
–
This pin is the positive terminal of the power supply input to
the circuit.
TD –
The resistor connected from this pin to V
EE
pin sets the time
delay from PWRGD-C going active to PWRGD-D going active.
TC –
The resistor connected from this pin to V
EE
pin sets the time
delay from PWRGD-B going active to PWRGD-C going active.
TB –
The resistor connected from this pin to V
EE
pin sets the time
delay from PWRGD-A going active to PWRGD-B going active.
RAMP –
This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected.
GATE –
This is the Gate Driver Output for the external N-Channel
MOSFET.
SENSE –
The current sense resistor connected from this pin to V
EE
Pin programs the servo control current limit and the circuit breaker
trip limit.
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
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