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參數(shù)資料
| 型號(hào)： | HV312NG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 電源管理 |
| 英文描述： | Sequencing Hotswap Controllers |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 618K |
| 代理商： | HV312NG |
1 Rev. D 04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302
HV312
__________________________________________________________________________________________________________________
Initial Release
Sequencing Hotswap Controllers
(Negative Supply Rail)
Features
-10V to 90V or +10V to +90V Operation
Four PWRGD Flags with Programmable Delays
Integrated “normally-on” Gate Clamp eliminates components
UV/OV Lock Out & Power-On-Reset (POR) for Debouncing
Sense resistor programmed Circuit Breaker & Servo Limit
Programmable Circuit Breaker Delay
Inrush control using either: Servo or Feedback Capacitor
Feedback to RAMP pin saves gate protection components
100ms Start Up Timeout Protection for Output Overload
Programmable Inrush Current di/dt Control
Programmable Auto-Retry (tens of seconds if desired)
Auto-Retry or Latched Operation
Application solution for input voltage step (diode “ORing”)
Enable through Open Drain interface to UV or OV
Low Power, 0.6mA Active Mode, 0.4mA Sleep Mode
Small SOIC-14 Package
Applications
-48V Telecom and Networking
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
Power Over LAN (IEEE802.3)
Distributed Power Systems
Power Supply Control
+48V Servers and SANs
Hotswap Control of Diode ORed Multiple Power Sources
Cooling Fan Systems
General Description
The HV302 and HV312 Hotswap Controllers perform current
limiting, circuit breaker protection, over and under voltage
detection power management functions during insertion of cards or
modules into live backplanes and connectors. They may be used
in systems where active control is implemented in the negative
lead of supplies ranging from -10V to -90V or +10V to +90V.
During initial power application the external pass device is held off
by a “normally-on” circuit that clamps its gate low. Thereafter
UV/OV and power-on-reset work together to suppress gate turn on
due to contact bounce. When stable connection has been
established for the duration of a programmed time delay, the
inrush current is controlled and limited to a programmed level
using one of two possible methods;
servo mode
or drain to ramp
feedback capacitor mode
. When charging of the load capacitor
is completed, the open drain PWRGD-A flag is asserted. Open
drain PWRGD-B, PWRGD-C and PWRGD-D flags are asserted
sequentially after the expiration of their respective programmed
time delays. Thereafter it transitions to a low power sleep mode
and continues to monitor current and input voltage. If full charging
of the load capacitor is not achieved within 100ms or the circuit
breaker is tripped at any time, the external pass device is turned
off and all four PWRGD flags are reset to the inactive state.
Thereafter a programmable auto-retry timer will hold the pass
device off to allow it to cool before resetting and initiating auto-
retry. The auto-retry can be disabled using a single resistor if
desired.
Typical Application Circuit and Waveforms
VDD
UV
OV
VEE
SENSE
GATE
RAMP
GND
-48V
IRF530
R4
R1
R2
R3
C1
10nF
Q1
HV302 / HV312
11
6
5
8
10
9
7
C2
1
Cload
+3.3V
DC/DC PWM
CONVERTER
COM
12
13
14
TB
TC
TD
2
3
4
+5V
DC/DC PWM
CONVERTER
COM
+12V
DC/DC PWM
CONVERTER
COM
-12V
DC/DC PWM
CONVERTER
COM
RTB
RTC
RTD
487k
6.81k
9.76k
0.0125
EN / EN
100uF
0.75nF
___
EN / EN
___
EN / EN
___
EN / EN
___
NOTES:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) set to 65V.
3. Current Limit set to -1A.
4. Circuit Breaker set to 8A.
PWRGD-A / PWRGD-A
________
PWRGD-B / PWRGD-B
________
PWRGD-C /PWRGD-C
________
PWRGD-D / PWRGD-D
________
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