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參數(shù)資料
| 型號： | HTG1390 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 4-bit Microcontroller |
| 中文描述： | 4位微控制器 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 427K |
| 代理商： | HTG1390 |
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OR A,XH
Machine code
Description
Logical OR immediate data to accumulator
0 1 0 0 0 1 0 0 0 0 0 0 d d d d
Data in the accumulator is logically ORed with the immediate data speci-
fied by the code.
ACC
←
ACC “OR” XH
Operation
OR A,[R1R0]
Machine code
Description
Logical OR accumulator with data memory
0 0 0 1 1 1 0 0
Data in the accumulator is logically ORed with the data memory ad-
dressed by the register pair “R1,R0”.
ACC
←
ACC “OR” M(R1,R0)
Operation
OR [R1R0],A
Machine code
Description
Logically OR data memory with accumulator
0 0 0 1 1 1 1 1
Data in the data memory addressed by the register pair “R1,R0” is logi-
cally ORed with the accumulator.
M(R1,R0)
←
M(R1,R0) “OR” ACC
Operation
OUT PA,A
Machine code
Description
Operation
Output accumulator data to port A
0 0 1 1 0 0 0 0
The data in the accumulator is transferred to port PA and latched.
PA
←
ACC
READ MR0A
Machine code
Description
Read ROM code of current page to M(R1,R0) and ACC
0 1 0 0 1 1 1 0
The 8-bit ROM code (current page) addressed by ACC and R4 is moved to
the data memory M(R1,R0) and the accumulator. The high nibble of the
ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is
loaded to the accumulator. The address of the ROM code is specified as be-
low:
Current page
→
ROM code address bit 11~8
ACC
→
ROM code address bit 7~4
R4
→
ROM code address bit 3~0
M(R1,R0)
←
ROM code (high nibble)
ACC
←
ROM code (low nibble)
Operation
HTG1390
Preliminary
23
17th Nov ’98
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