參數(shù)資料
型號： HT95L300-100QEP-A
廠商： Holtek Semiconductor Inc.
英文描述： LCD Type Phone 8-Bit MCU
中文描述： 液晶式電話8位微控制器
文件頁數(shù)： 16/42頁
文件大?。?/td> 768K
代理商： HT95L300-100QEP-A
HT95L100/10P
Rev. 0.10
16
October 1, 2002
Preliminary
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are imple-
mented in the telephone controller series. The
Timer/Event Counter 0 and Timer/Event Counter 1 con-
tain 16-bits programmable count-up counter and the
clock may come from an external source or internal
source. For TMR0 internal source is instruction clock
(systemclock/4).ForTMR1internalsourceis32768Hz.
Using the 32768Hz clock or instruction clock, there is
only one reference time-base. The external clock input
allows the user to count external events, measure time
intervals or pulse width, or generate an accurate time
base.
There are 3 registers related to Timer/Event Counter 0;
TMR0H, TMR0L, TMR0C. Writing TMR0L only writes
the data into a low byte buffer, but writing TMR0H simul-
taneously writes the data along with the contents of the
low byte buffer into the Timer/Event Counter 0 preload
register (16-bit). The Timer/Event Counter 0 preload
register is changed by writing TMR0H operations. Writ-
ing TMR0L will keep the Timer/Event Counter 0 preload
register unchanged.
Reading TMR0H latches the TMR0L into the low byte
buffer to avoid a false timing problem. Reading TMR0L
returns the contents of the low byte buffer. In other
words, the low byte of the Timer/Event Counter 0 can
not be read directly. It must read the TMR0H first to
make the low byte contents of Timer/Event Counter 0 be
latched into the buffer.
There are 3 registers related to the Timer/Event Counter
1; TMR1H, TMR1L, TMR1C. The Timer/Event Counter
1 operates in the same manner as the Timer/Event
Counter 0.
The TMR0C is the Timer/Event Counter 0 control regis-
ter, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options as the
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Timer/Event Counter 0/1
Register
Label
Bits
R/W
Function
TMR0C
(0EH)
TMR1C
(11H)
0~2
RO
Unused bit, read as 0
TE
3
RW
To define the TMR0/TMR1 active edge of timer
For event count or Timer mode
(0=active on low to high; 1=active on high to low)
For pulse width measurement mode
(0=measures low pulse width; 1=measures high pulse width)
TON
4
RW
To enable/disable timer counting (0=disabled; 1=enabled)
5
RO
Unused bit, read as 0
TM0
TM1
6
7
RW
To define the operating mode
Bit 7, 6=01, Event count mode (external clock)
Bit 7, 6=10, Timer mode
Bit 7, 6=11, Pulse width measurement mode
Bit 7, 6=00, Unused
Register
Bits
R/W
Function
TMR0H (0CH)
0~7
RW
Timer/Event Counter 0 higher-order byte register
TMR0L (0DH)
0~7
RW
Timer/Event Counter 0 lower-order byte register
TMR1H (0FH)
0~7
RW
Timer/Event Counter 1 higher-order byte register
TMR1L (10H)
0~7
RW
Timer/Event Counter 1 lower-order byte register
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