參數(shù)資料
型號: HT95L300-100QEP-A
廠商: Holtek Semiconductor Inc.
英文描述: LCD Type Phone 8-Bit MCU
中文描述: 液晶式電話8位微控制器
文件頁數(shù): 11/42頁
文件大?。?/td> 768K
代理商: HT95L300-100QEP-A
HT95L100/10P
Rev. 0.10
11
October 1, 2002
Preliminary
Register
Bits
Label
R/W
Function
INTC0
(0BH)
0
EMI
RW
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI
RW
Controls the external interrupt (1=enabled; 0=disabled)
2
ET0I
RW
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
RW
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4
EIF
RW
External interrupt request flag (1=active; 0=inactive)
5
T0F
RW
Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
RW
Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
RO
Unused bit, read as 0
INTC1
(1EH)
0
RO
Unused bit, read as 0
1
ERTCI
RW
Control the real time clock interrupt (1=enable; 0=disable)
2
EDRI
RW
Control the dialer I/O interrupt (1=enable; 0=disable)
3
RO
Unused bit, read as 0
4
RO
Unused bit, read as 0
5
RTCF
RW
Internal real time clock interrupt request flag (1=active; 0=inactive)
6
DRF
RW
Internal dialer I/O interrupt request flag (1=active: 0=inactive)
7
RO
Unused bit, read as 0
The Timer/Event Counter 1 interrupt is generated by a
timeout overflow and the interrupt request flag T1F will
be set. When the Timer/Event Counter 1 interrupt is en-
abled, the stack is not full and the T1F bit is set, a sub-
routine call to location 0CH will occur. The interrupt
request flag T1F and EMI bits will be cleared to disable
further interrupts.
The real time clock interrupt is generated by a 1Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a sub-
routine call to location 14H will occur. The interrupt re-
quest flag RTCF and EMI bits will be cleared to disable
other interrupts.
The dialer I/O interrupt is triggered by any edge transi-
tion onto HKS pin or a falling edge transition onto HDI
pin or a rising edge transition onto HFI pin, the interrupt
request flag DRF will be set. When the dialer I/O inter-
rupt is enabled, the stack is not full and the DRF is set, a
subroutine call to location 18H will occur. The interrupt
request flag DRF and EMI bits will be cleared to disable
other interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 interrupt
2
08H
Timer/Event Counter 1 interrupt
3
0CH
Real time clock interrupt
4
14H
Dialer I/O interrupt
5
18H
Priority of the interrupt
EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to con-
trol the enabling/disabling of interrupts. These bits pre-
vent the requested interrupt from being serviced. Once
the interrupt request flags (EIF, T0F, T1F, RTCF, DRF)
are set by hardware or software, they will remain in the
INTC0 or INTC1 registers until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program should not use the
CALL subroutine within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
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