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參數(shù)資料
| 型號(hào)： | HT9172 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | DTMF Receiver |
| 中文描述： | 雙音多頻接收器 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 124K |
| 代理商： | HT9172 |
HT9172
Rev. 1.00
5
March 30, 2006
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Figure 1. Test Circuit
Functional Description
Overview
The HT9172 tone decoder consists of three band pass
filters and two digital decode circuits to convert a DTMF
tone into a digital code output.
The device contains an operational amplifier to adjust
the input signal level as shown in Figure 2.
The pre-filter is a band rejection filter which will reject
frequencies between 350Hz to 400Hz.
The low group filter, filters the low group frequency sig-
nal output whereas the high group filter, filters the high
group frequency signal output.
Each filter output is followed by a zero-crossing detector
with incorporates hysteresis. When the signal amplitude
at the output exceeds a specified level, it is transferred
to a full swing logic signal.
When the input signal is recognized as an effective
DTMF tone, the DV line will go high, and the corre-
sponding DTMF tone code will be generated.
Steering Control Circuit
The steering control circuit is used to measure the effec-
tive signal duration and for protecting against valid sig-
nal drop out. This is achieved using an analog delay
which is implemented using an external RC time-con-
stant, controlled by the output line EST.
The timing diagram is shown in Figure 3. The EST pin is
normally low and will pull the RT/GT pin low via the ex-
ternal RC network. When a valid tone input is detected,
the EST pin will go high, which will in turn pull the RT/GT
pin high through the RC network.
When the voltage on RT/GT rises from 0 to V
TRT
, which
is 2.35V for a 5V power supply, the input signal is effec-
tive, and the corresponding code will be generated by
the code detector. After D0~D3 have been latched, DV
will go high. When the voltage on RT/GT falls from VDD
to V
TRT
, i.e. when there is no input tone, the DV output
will go low, and D0~D3 will maintain their present data
until a next valid tone input is produced.
By selecting suitable external RC values, the minimum
acceptable input tone duration, t
ACC
, and the minimum
acceptable inter-tone rejection, t
IR
, can be set. The values
of the external RC components, can be chosen using the
following formula. Also refer to Figure 5 for details.
t
ACC
=t
DP
+t
GTP
;
t
IR
=t
DA
+t
GTA
;
where
t
ACC
: Tone duration acceptable time
t
DP
: EST output delay time ( L
t
GTP
: Tone present time
t
IR
: Inter-digit pause rejection time
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Figure 2. Amplifier Input Application Circuits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT9200 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:DTMF Generators |
| HT92000526-5 | 制造商:Rennsteig 功能描述:PACK CON III FEM |
| HT9200A | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:DTMF Generators |
| HT9200A(8SOIC) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tone Telephone Dialer |
| HT9200A_04 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:DTMF Generators |
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