Pin Assignment
Pin Description
Pin Name
I/O
Internal
Connection
Description
VP
I
Operational
Amplifier
Operational amplifier non-inverting input
VN
I
Operational amplifier inverting input
GS
O
Operational amplifier output terminal
VREEF
O
VREF
Reference voltage output, normally V
DD
/2
X1
I
oscillator
The system oscillator consists of an inverter, a bias resistor and the required
on-chip load capacitor.
A standard 3.579545MHz crystal connected to the X1 and X2 terminals imple-
ments the oscillator function.
X2
O
PWDN
I
CMOS IN
Pull-low
Active high. This enables the device to go into its power down mode and inhibits
the oscillator. This pin input is pulled low internally.
INH
I
CMOS IN
Pull-low
Active high. This inhibits the detection of tones representing characters A, B, C
and D. This pin input is pulled low internally.
VSS
Negative power supply, ground
OE
I
CMOS IN
Pull-high
D0~D3 output enable, active high
D0~D3
O
CMOS OUT
Tristate
Received data output terminals
OE= H : Output enable
OE= L : High impedance
DV
O
CMOS OUT
Data valid output.
When the device has received a valid DTMF tone, this line will go high; other-
wise it remains low.
EST
O
CMOS OUT
Early steering output - see Functional Description
RT/GT
I/O
CMOS IN/OUT
Tone acquisition time and release time can be set through connection with ex-
ternal resistor and capacitor.
VDD
Positive power supply, 2.5V~5.5V for normal operation
HT9172
Rev. 1.00
2
March 30, 2006
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