參數(shù)資料
型號(hào)： HT86R192
廠商： Holtek Semiconductor Inc.
英文描述： Voice Synthesizer 8-Bit OTP MCU
中文描述： 語(yǔ)音合成器8位微控制器檢察官辦公室
文件頁(yè)數(shù)： 17/44頁(yè)
文件大?。?/td> 287K
代理商： HT86R192
HT86R192
Rev. 0.00
17
October 23, 2006
Preliminary
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
When a system power up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The function unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the stack
Timer/Event Counter 0/1
There are four timer counters are implemented in the
HT86R192. The Timer/Event Counter 0 and 1 contain
16-bit programmable count-up counters whose clock
may come from an external source or the system clock
divided by 4 (T1). Using the internal instruction clock
(T1), there is only one reference time base. The external
clock input allows the user to count external events,
measure time intervals or pulse width, or to generate an
accurate time base.
There are three registers related to Timer/Event Counter
0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing
to TMR0Lonly writes the data into a low byte buffer. Writ-
ing to TMR0H will write the data and the contents of the
low byte buffer into the Timer/Event Counter 0 preload
register (16-bit) simultaneously. The Timer/Event Coun-
ter 0 preload register is changed only by a write to
TMR0H operation. Writing to TMR0L will keep the
Timer/Event Counter 0 preload register unchanged.
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid false timing problems. Reading the
TMR0L only returns the value from the low byte buffer
which may be a previously loaded value. In other words,
thelowbyteofTimer/EventCounter0cannotbereaddi-
rectly. It must read the TMR0H first to ensure that the
low byte contents of Timer/Event Counter 0 are latched
into the buffer.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L(10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same man-
ner as Timer/Event Counter 0.
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Reset Circuit
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Reset Configuration
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Timer/Event Counter 0/1
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