參數(shù)資料
型號(hào)： HT82V842A
廠商： Holtek Semiconductor Inc.
英文描述： 10-Bit 20MSPS CCD Analog Signal Processor
中文描述： 10位20MSPS CCD模擬信號(hào)處理器
文件頁(yè)數(shù)： 7/18頁(yè)
文件大小： 178K
代理商： HT82V842A
HT82V842A
Rev. 1.00
7
January 2, 2006
A/D Input
Digital Output Code
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Full Scale
1
1
1
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
:
0
1
1
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
:
:
:
Zero Scale
0
0
0
0
0
0
0
0
0
0
ADC Data Output (Coding: Straight Binary)
A/DConverterOutputCode(Mode1RegisterD5=1)
The format of an ADC digital output is a straight binary.
When in the input zero reference voltage, the output
code will be all zero and when the input is a full scale
voltage, the output code will be all one.
Clock, Pipeline Delay, Digital Data Output Timing
The ADCK input is used for an A/D conversion. The
ADC input signal is sampled at the falling edge of the
ADCK input and 10 bits parallel data is output at the ris-
ing edge of the ADCK input after a 5.5 clock of pipeline
delay.
High-Z Control of ADC Digital Output
ADC digital outputs become High-Z under the following
conditions:
SettheADCoutputbittoone.(Mode1registerD2=1)
Set the STBY pin to low
Set the power control bit to one (Mode 1 register
D0=1)
Miscellaneous Function
(ADC Direct Input, ADIN Mode)
The direct input path to the ADC or the PGAis achieved
by means of a register setting. The selectable paths are
as follows:
Function disable (default, Mode 1 register D5=0,
D4=0)
ADINinputtothePGA(Mode1registerD5=0,D4=1)
ADIN input to the PGA (Mode 1 register D5=1,
D4=Don t care)
The BLK, SHD and SHR inputs are ignored at the ADIN
mode.
Power Down Mode
The power down mode can be set either by register set-
ting or by the STBY pin.
Monitor Output
When setting Mode 2 (D1 and D0), the signal from
MONOUT is selectable. The alternatives are OFF, CDS
output, PGA output or REFIN/CCDIN output. The
MONOUT pin gain is fixed to 0dB regardless of the gain
control register setting when the CDS output is selected.
The MONOUT level becomes V
COM
at zero reference
level. The signals are output in reverse for the CCD in-
put.
Polarity Inversion
The following input polarities can be inverted by register
setting:
ADCK (A/D converter sampling clock, Mode 1 register
D6)
SHR and SHD (CDS sampling clock, Mode 2 register
D3 and D2)
BLK, OBP, CCDCLP and ADCLP (Mode 2 register D3
and D2)
Data Output Clock
The ADCK input or the OUTCK input is selectable as an
ADC data output clock.
Serial Interface Circuit
The internal registers of the HT82V842A are controlled
by a 3-wire serial interface. The data is a 16-bit length
serial data that consists of a 2-bit operation code, 4 bits
address and 10 bits data. Each bit is fetched at the rising
edge of the CS input. Keep CS to high when not access
HT82V842A. It is prohibited to write to a non-defined ad-
dress. When a data length is below 16 bits, the data is
not executed.
Registers
The HT82V842Ahas 10 bits 7 registers that control the
operations. All registers are write only, the serial regis-
ters are written by the serial interface.
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