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參數(shù)資料
| 型號： | HT82V842A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 10-Bit 20MSPS CCD Analog Signal Processor |
| 中文描述： | 10位20MSPS CCD模擬信號處理器 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 178K |
| 代理商： | HT82V842A |
HT82V842A
Rev. 1.00
5
January 2, 2006
Functional Description
CDS (Correlated Double Sampling) Circuit
Connect the CCDIN pin to the CCD sensor thru a capac-
itor. Connect also the REFIN pin to V
SS
thru a capacitor.
The CDS circuit holds the pre-charge voltage of the
CCD at SHR pulse and do sampling of the CCD pixel
data at SHD pulse. Correlated noise is removed by sub-
tracting the pre-charge voltage from the pixel data level.
CDS could choose a gain setting from 0, 6.02, 12 or
1.94dB (Mode 3, register D4 and D5 bits). A CDS gain
is controlled by PGA gain. It is recommended to in-
crease the CDS gain then increase the PGA gain to re-
duce the noise level.
Clamp Circuits
DC clamp
The DC level of the CCDIN/REFIN input is fixed by an
internal DC clamp circuit. The DC level of the
C-coupled CCD signal at the CDS input is set to
CLPCAP by the internal DC clamp circuit. The clamp
switches are usually turned on at the black level cali-
bration period. The CLPCAP pin connects to V
SS
thru
a 0.1 F capacitor.
ADIN signal clamp
Clamp operation can also be used for the ADIN path.
The clamp voltage is different from the CCDIN/REFIN
signal and it could be turned off by register setting. At
ADIN signal to ADC mode, the ADCLP signal con-
trols the clamp circuit . Black level calibration circuit
is also controlled by ADCLP at ADIN signal to PGA
mode.
Clamp control
Clampcurrent(Mode2registerD7).Chargecurrent
can select normal or fast clamp.
Clamp target (Mode 2 register D5 and D4), input
signals (REFIN and CCDIN) to be clamped are
selectable. The clamp function can be turned off.
Black Level Cancel Circuit
The purpose of a black level cancel circuit is to control
the DC level of the PGA input. The ADC output code at
an optical black period may correspond to the black
level code set up by the register. Ablack level code of (1
to) 16 to 127 LSB is available (the default is 64 LSB).
While the OBP pin is active a black level cancel loop is
established. In the loop, a comparison is made between
the ADC output code and the black level code, the result
controls the voltage of the OBCAPcapacitor. Hence, the
OBCAP voltage settles gradually and the signal level of
the optical black period corresponds to the established
value.
The following conditions will reset the OBCAP capaci-
tor:
Set the black level reset register to 1 (Mode 1 regis-
ter D1=1).
Set the RESET pin to low
Power down by STBY pin or register control
The DC clamping (CCDCLP) is allowed while the OBP
pin is low. The black level cancellation is available at
ADIN signal to PGA mode. The black level cancella-
tion is available at the ADCLP period in this mode. The
clamping function and black level canceling function are
done simultaneously.
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