HT82K95E/HT82K95A
Rev. 1.20
16
October 24, 2005
ofTMR0C/TMR1C)shouldbesetto1.Inthepulsewidth
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is completed. But in
the other two modes the TON can only be reset by in-
structions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the oper-
ation mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preloadreg-
ister will also reload that data to the Timer/Event Coun-
ter 0/1. But if the Timer/Event Counter 0/1 is turned on,
data written to it will only be kept in the Timer/Event
Counter 0/1 preload register. The Timer/Event Counter
0/1 will still operate until overflow occurs (a Timer/Event
Counter 0/1 reloading will occur at the same time).
When the Timer/Event Counter 0/1 (reading
TMR0/TMR1) is read, the clock will be blocked to avoid
errors. As clock blocking may results in a counting error,
this must be taken into consideration by the program-
mer.
Input/Output Ports
There are 32 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to the data memory of [12H], [14H], [16H] and
[18H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOVA,[m] (m=12H,
14H, 16H or 18H). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS/NMOS/PMOS output
or Schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically under soft-
ware control. To function as an input, the corresponding
latch of the control register must write a 1 . The input
source also depends on the control register. If the con-
trol register bit is 1 , the input will read the pad state. If
the control register bit is 0 , the contents of the latches
will move to the internal bus. The latter is possible in the
read-modify-write
CMOS/NMOS/PMOS configurations can be selected
(NMOS and PMOS are available for PA only). These
controlregistersaremappedtolocations13H,15H,17H
and 19H.
instruction. For output function,
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of all the I/O ports have the capability of wak-
ing up the device.
There are pull-high (PA only) options available for I/O
lines. Once the pull-high option of an I/O line is selected,
the I/O line have pull-high resistor. Otherwise, the
pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
,
-
.
- & /
- 0
.
0
.
0
.
0
1
2
3
4
#
3
4
#
(
"
)
5
6 "
+ !
- 0
-
"
3
3
5
6 "
"
+ !
Input/Output Ports