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參數(shù)資料
| 型號： | HT82K68E-L |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Multimedia Keyboard Encoder 8-Bit MCU |
| 中文描述： | 多媒體鍵盤編碼器8位微控制器 |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HT82K68E-L |
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HT82K68E-L/HT82K68A-L
Rev. 1.00
9
August 9, 2007
Interrupt
The device provides an internal timer counter interrupt
and an external interrupt shared with PC2. The interrupt
control register (INTC;0BH) contains the interrupt
control bits to set not only the enable/disable status but
also the interrupt request flags.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
schememaypreventanyfurtherinterruptnesting.Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupt have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack followed by
a branch to a subroutine at the specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which corrupt the desired control sequence, the
contents should be saved in advance.
The internal timer counter interrupt is initialized by set-
ting the timer counter interrupt request flag (T0F; bit 5 of
INTC), which is normally caused by a timer counter
overflow. When the interrupt is enabled, and the stack is
notfullandtheT0Fbitisset,asubroutinecalltolocation
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The external interrupt is shared with PC2. The external
interrupt is activated, the related interrupt request flag
(EIF; bit4 of INTC) is then set. When the interrupt is en-
abled, the stack is not full, and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will also be
cleared to disable other interrupts.
The external interrupt (PC2) can be triggered by a high
to low transition, or a low to high transition of the PC2,
which is dependent on the output level of the PE0.
When PE0 is output high, the external interrupt is trig-
gered by a low to high transition of the PC2. When PE0
is output low, the external interrupt is triggered by a high
to low transition of PC2.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or if no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is
set by executing a HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6, 7
Unused bit, read as 0
Status (0AH) Register
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Control the external interrupt
2
ET0I
Controls the timer counter interrupt (1= enabled; 0= disabled)
3
Unused bit, read as 0
4
EIF
External interrupt flag
5
T0F
Internal timer counter request flag (1= active; 0= inactive)
6, 7
Unused bit, read as 0
INTC (0BH) Register
相關PDF資料 |
PDF描述 |
|---|---|
| HT82K68A | 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片，用于多I/O口及多媒體器件) |
| HT82K68E | 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片，用于多I/O口及多媒體器件) |
| HT82K68 | Multimedia Keyboard Encoder OTP |
| HT82K94A | USB Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K94E | USB Multimedia Keyboard Encoder 8-Bit MCU |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HT82K68E-L_09 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K68E-L_11 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K70A-L | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
| HT82K70E-L | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit OTP MCU |
| HT82K70E-L_11 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
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