HT82K68E-L/HT82K68A-L
Rev. 1.00
12
August 9, 2007
Reset
There are three ways in which a reset can occur:
RESET reset during normal operation
RESET reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the program counter and stack pointer,
leaving the other circuits to remain in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the initial condi-
tion when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be-
tween different chip resets .
TO
PDF
RESET Conditions
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
0
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tempowersuporwhenitawakesfromtheHALTstate.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RESET pin, the SST delay is disabled.
Any wake-up from HALT will enable the SST delay.
The functional unit chip reset status is shown below.
Program Counter
000H
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer counter
Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the stack
Timer Counter
A timer counter (TMR) is implemented in the
microcontroller. The timer counter contains an 8-bit
programmable count-up counter and the clock may
come from the system clock divided by 4.
Using the internal instruction clock, there is only one ref-
erence time-base.
There are two registers related to the timer counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer counter preload register
and reading TMR gets the contents of the timer counter.
The TMRC is a timer counter control register, which de-
fines some options.
&
:
$
& &
Reset Timing Chart
Reset Circuit
-
-
:
. &
= ! #
@
:
&
:
&
. &
-
&
Reset Configuration
Bit No.
Label
Function
0~3
Unused bit, read as "0"
4
TON
To enable/disable timer counting (0= disabled; 1= enabled)
5
Unused bit, read as "0"
6
7
TM0
TM1
10= Timer mode (internal clock)
TMRC (0EH) Register