參數(shù)資料
型號(hào)： HT82A821R
廠商： Holtek Semiconductor Inc.
英文描述： USB Audio MCU
中文描述： USB音頻控制器
文件頁(yè)數(shù)： 18/39頁(yè)
文件大?。?/td> 275K
代理商： HT82A821R
HT82A821R
Rev. 1.10
18
June 29, 2007
Bit No.
Label
R/W
Power-on
Functions
0
ASET
R/W
0
This bit is used to configure the SIE automatically change the device ad-
dress by the value stored in the AWR register. When this bit is set to 1
by firmware, the SIE will update the device address by the value stored
in the AWR register after PC host is successfully read the data from de-
vice by IN operation. Otherwise, when this bit is cleared to 0 , the SIE
will update the device address immediately after an address is written to
the AWR register. So, in order to work properly, firmware has to clear
this bit after next valid SETUP token is received.
1
ERR
R/W
0
This bit is used to indicate there are some errors occurred during the
FIFO0 is accessed. This bit is set by SIE and should be cleared by firm-
ware.
2
OUT
R/W
0
This bit is used to indicate there are OUT token (except the OUT zero
length token) has been received. The firmware clears this bit after the
OUT data has been read. Also, this bit will be cleared by SIE after the
next valid SETUP token is received.
3
IN
R
0
This bit is used to indicate the current USB receiving signal from PC host
is IN token.
4
NAK
R
0
This bit is used to indicate the SIE is transmitted NAK signal to host in re-
sponse to PC host IN or OUT token.
5
CRCF
R/W
0
Error condition failure flag include CRC, PID, no integrate token error,
CRCF will be set by hardware and the CRCF need to be cleared by firm-
ware.
6
EOT
R
1
Token package active flag, low active.
7
NMI
R/W
0
NAK token interrupt mask flag. If this bit set, when device sent a NAK to-
ken to host, the interrupt will not happen. Otherwise when this bit is
cleared, device sent a NAK token to host will enter the interrupt
sub-routine.
SIES (25H) Register
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
wanted endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No.
Label
R/W
Power-on
Functions
0
REQUEST
R/W
0
After setting others status of desired one, FIFO can be requested by set-
ting this bit high active. After work has been done, this bit must be set
low.
1
TX
R/W
0
To represent the direction and transition end MCU accesses, When be-
ing set logic 1, MCU wants to write data to FIFO. After the work being
done, this bit must be set logic 0 before terminating request to represent
transitionend.Forreadingaction,thisbitmustbesetlogic0torepresent
MCU want to read and must be set logic 1 after the work done.
2
CLEAR
R/W
0
TorepresentMCUclearrequestedFIFO,eventheFIFOisnotready.Af-
ter clearing the FIFO, USB interface will send force_tx_err to tell Host
that data under-run if Host want to read data.
3
R
0
Undefined bit, read as 0 .
4
ISOEN-
R/W
0
To enable the isochronous pipe interrupt.
5
SETCMD
R/W
0
To show that the data in FIFO is setup command. This bit will last this
state until next one entering the FIFO.
6
READY
R
0
To tell that the desired FIFO is ready to work.
7
LEN0
R
0
To tell that host sent a 0-sized packet to MCU. This bit must be cleared
by read action to corresponding FIFO.
USB MISC (26H) Register
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