HT82A821R
Rev. 1.10
16
June 29, 2007
USB Interface
The HT82A821R have 3 Endpoints (EP0 ~EP2). EP0 supports Control transfer. EP1 supports Interrupt transfer. EP2
supports Isochronous transfer.
These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H ), SIES (25H), MISC (26H),
SETIO (27H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH) used for the USB function.
The FIFO size of each FIFO is 8 byte (FIFO0), 8 byte (FIFO1), 384 byte (FIFO2), and total are 400 bytes.
URD (bit7 of USC) is USB reset signal control function definition bit.
Bit No.
Label
R/W
Reset
Functions
0
SUSP
R
0
Read only, USB suspend indication. When this bit is set to 1 (set
by SIE), it indicates the USB bus enters suspend mode. The USB in-
terrupt is also triggered on changing from low to high of this bit.
1
RMWK
R/W
0
USB remote wake-up command. It is set by MCU to force the USB
host leaving the suspend mode.
2
URST
R/W
0
USB reset indication. This bit is set/cleared by USB SIE. This bit is
used to detect USB reset event on USB bus. When this bit is set to
1 ,thisindicatesanUSBresetisoccurredandanUSBinterruptwill
be initialized.
3
RESUME
R
0
USB resume indication. When the USB leaves suspend mode, this
bit is set to 1 (set by SIE). When the RESUME is set by SIE, an in-
terrupt will be generated to wake-up the MCU. In order to detecting
the suspend state, MCU should set USBCKEN and clear SUSP2 (in
UCC register) to enable the SIE detecting function. The RESUME
will be cleared while the SUSP is going 0 . When MCU is detecting
the SUSP, the RESUME (causes MCU to wake-up) should be re-
membered and token into consideration.
4
V33O
R/W
0
0/1: Turn-off/on V33O output
5~6
Undefined bit, read as 0 .
7
URD
R/W
1
USB reset signal control function definition
1: USB reset signal will reset MCU
0: USB reset signal cannot reset MCU
USC (20H) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
serialbus(USB).Theendpointrequestflags(EP0F,EP1F,EP2F)areusedtoindicatewhichendpointsareaccessed.If
an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if USB in-
terrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag
has to be cleared to 0 by software.
Bit No.
Label
R/W
Reset
Functions
0
EP0F
R/W
0
When this bit is set to 1 (set by SIE). It indicates the endpoint 0 is
accessed and an USB interrupt will occur. When the interrupt has
been served, this bit should be cleared by software.
1
EP1F
R/W
0
When this bit is set to 1 (set by SIE). It indicates the endpoint 1 is
accessed and an USB interrupt will occur. When the interrupt has
been served, this bit should be cleared by software.
2
EP2F
R/W
0
When this bit is set to 1 (set by SIE). It indicates the endpoint 2 is
accessed and an USB interrupt will occur. When the interrupt has
been served, this bit should be cleared by software.
3~7
Undefined bit, read as 0 .
USR (21H) Register