參數(shù)資料
型號： HT82A821R_07
廠商： Holtek Semiconductor Inc.
英文描述： USB Audio MCU
中文描述： USB音頻控制器
文件頁數(shù)： 14/39頁
文件大?。?/td> 275K
代理商： HT82A821R_07
HT82A821R
Rev. 1.10
14
June 29, 2007
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C or TMR1C) should be set to 1. In
the pulse width measurement mode, TON is automati-
cally cleared after the measurement cycle is completed.
But in the other two modes, the TON can only be reset
by instructions. The overflow of the Timer/Event Coun-
ter 0/1 is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ET0I or ET1I dis-
ables the related interrupt service.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may re-
sults in a counting error. Blocking of the clock should be
taken into account by the programmer.
Input/Output Ports
There are 8 bidirectional input/output lines (PA) in the
microcontroller, which are mapped to the data memory
of [12H] respectively. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, that is, the inputs must be
ready at the T2 rising edge of instruction MOV A,[m]
(m=12H). For output operation, all the data is latched
and remains unchanged until the output latch is rewrit-
ten.
Each I/O line has its own control register (PAC) to con-
trol the input/output configuration. With this control reg-
ister, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically (i.e., on-the-fly) under software control. To
function as an input, the corresponding latch of the con-
trol register must write 1 . The input source also de-
pends on the control register. If the control register bit is
1 theinputwillreadthepadstate.Ifthecontrolregister
bit is 0 the contents of the latches will move to the in-
ternal bus. The latter is possible in the Read-modify-
write instruction. For output function, CMOS configura-
tions can be selected. The control register is mapped to
location 13H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or in a floating state (depending on the
pull-high/low options). Each bit of these input/output
latches can be set or cleared by SET [m].i and CLR
[m].i (m=12H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
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Input/Output Ports
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