參數(shù)資料
型號(hào): HT82A821R_07
廠商: Holtek Semiconductor Inc.
英文描述: USB Audio MCU
中文描述: USB音頻控制器
文件頁(yè)數(shù): 12/39頁(yè)
文件大?。?/td> 275K
代理商: HT82A821R_07
HT82A821R
Rev. 1.10
12
June 29, 2007
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset,WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
The registers status are summarized in the following table.
Register
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
000H
000H
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
USC
1000 0000
uuxx uuuu
10xx 0000
10xx 0000
10xx uuuu
1000 0u00
1000 0u00
USR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
00uu 0000
00uu 0000
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SETIO
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
DAC_LIMIT_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
DAC_LIMIT_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
DAC_WR
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
Note:
* stands for warm reset
u stands for unchanged
x stands for unknown
_ stands for undefined
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