參數(shù)資料
型號: HT6576A
廠商: Holtek Semiconductor Inc.
英文描述: Advanced SCSI CHIP
中文描述: 高級SCSI芯片
文件頁數(shù): 5/14頁
文件大?。?/td> 412K
代理商: HT6576A
BIT 4: E NABLE PARITY INTE RRUPT
When set, this bit causes the IRQ signal to be asserted if a parity error is detected.
BIT 3: E NABLE E OP INTE RRUPT
When set, this bit causes the IRQ signal to be asserted if E OP is received from the DMA controller.
BIT 2: MONITOR BUSY
When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at
least a bus settle delay.
BIT 1: DMA MODE
BIT 0: Arbitrate
When set, this bit starts the arbitration process.
Address 3: Target command register
7 6 5 4 3 2 1 0
LAST BYTE
X
X
X
ASSE RT
RE Q
ASSE RT
MSG
ASSE RT
C/D
ASSE RT
I/O
R R/W R/W R/W R/W
BIT 7: LAST BYTE SE ND (RE AD ONLY)
BIT 3: ASSE RT RE Q
WHE N SE T, THE REQ SIGNAL IS ASSE RTED ON THE SCSI BUS (IN TARGE T MODE )
BIT 2: ASSE RT MSG
WHE N SE T, THE MSG SIGNAL IS ASSE RTED ON THE SCSI BUS (IN TARGE T MODE )
BIT 1: ASSE RT C/D
WHE N SE T, THE C/D SIGNAL IS ASSE RTED ON THE SCSI BUS (IN TARGE T MODE )
BIT 0: ASSE RT I/O
WHE N SE T, THE I/O SIGNAL IS ASSE RTED ON THE SCSI BUS (IN TAGRTE MODE )
Address 4: Current SCSI Bus Register
RE AD
7 6 5 4 3 2 1 0
RST
BSY
RE Q
MSG
C/D
I/O
SE L
DBP
WRITE –SE LE CT E NABLE RE GISTE R
7 6 5 4 3 2 1 0
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
HT6576A
5
14th J uly ’97
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