參數(shù)資料
型號(hào): HT6116-70
廠商: Holtek Semiconductor Inc.
英文描述: CMOS 2K??8-Bit SRAM
中文描述: 的CMOS 2K??8位SRAM
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 305K
代理商: HT6116-70
(6) OE is continuously low (OE =V
IL
).
(7) D
OUT
is at the same phase of the write data of this write cycle.
(8) D
OUT
is the read data of the next address.
(9) If CS is low during this period, I/O pins are in the output state; then the data input
signals of the opposite phase to the outputs must not be applied to them.
(10) Transition is measured
±
500mV from the steady state.
Data Rentention Characteristics
(Ta=–40
°
C to +85
°
C)
Symbol
Parameter
Conditions
Min.
Max. Unit
V
DR
V
DD
for Data Retention
CS
V
DD
-0.2V
2
5.5
V
I
CCDR
Data Retention Current
V
DD
=3V, CS
V
DD
-0.2V
V
IN
V
DD
-0.2V or V
IN
0.2V
50
μ
A
t
CDR
Chip Disable Data Retention Time See Retention Timing
0
ns
t
R
Operation Recovery Time
See Retention Timing
t
RC
*
ns
*t
RC
=Read Cycle Time
Low V
DD
Data Retention Timing
HT6116-70
8
3rd J uly ’97
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