參數(shù)資料
型號(hào)： HT48RB8
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit USB Type OTP MCU
中文描述： 8位微控制器的USB型檢察官辦公室
文件頁(yè)數(shù)： 12/45頁(yè)
文件大?。?/td> 281K
代理商： HT48RB8
HT48RB8
Rev. 1.30
12
February 10, 2003
Once the internal WDT oscillator (RC oscillator with a
period of 31 s/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
cangivedifferenttime-outperiods.IfWS2,WS1,andWS0
are all equal to 1, the division ratio is up to 1:128, and the
maximum time-out period is 1s/5V seconds. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operates in the same manner
except that in the HALT state the WDT may stop count-
ing and lose its protecting purpose. In this situation the
logic can only be restarted by external logic. The high
nibble and bit 3 of the WDTS are reserved for user s de-
fined flags, which can only be set to
(WDTS.7~WDTS.3).
10000
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-
tor (RTC OSC) is strongly recommended, since the HALT
will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO . But in the HALT
mode, the overflow will initialize a warm reset and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted;externalreset(alowleveltoRES),softwarein-
structionanda HALT instruction.Thesoftwareinstruc-
tion include
CLR WDT
and the other set
CLR
WDT1 and CLR WDT2 . Of these two types of instruc-
tion, only one can be active depending on the ROM
code option
CLR WDT times selection option . If the
CLR WDT is selected (i.e. CLRWDT times equal one),
any execution of the CLR WDT instruction will clear
the WDT. In the case that CLR WDT and CLR WDT
are chosen (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the WDT; other-
wise,theWDTmayresetthechipasaresultoftime-out.
The time-out periods defined in WDTS can used as
wake-up period in the Mouse Hardware wake-up func-
tion. Please reference to Mouse Hardware Wake-up
function description.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PD flags are ex-
amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the CLR WDT instruction and is set when executing
the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
thePCandSP;theothersremainintheiroriginalstatus.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
devicebymaskoption.AwakeningfromanI/Oportstim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
1 before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
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