參數(shù)資料
型號: HT48R50A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 32/50頁
文件大?。?/td> 345K
代理商: HT48R50A-1
Mnemonic
Description
Instruction
Cycle
Flag
Affected
Table Read
TABRDC [m]
TABRDL [m]
Read ROM code (current page) to data memory and
TBLH
ReadROMcode(lastpage)todatamemoryandTBLH
2
(1)
2
(1)
None
None
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
(1)
1
(1)
1
1
1
1
(1)
1
1
None
None
None
TO,PD
TO
(4)
,PD
(4)
TO
(4)
,PD
(4)
None
None
TO,PD
Note: x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
: Flag is affected
: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
for one more cycle (four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be de-
layedforonemorecycle(foursystemclocks).Otherwisetheoriginalinstructioncycleisun-
changed.
(3)
:
(1)
and
(2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by
executingtheCLRWDT1orCLRWDT2instruction,theTOissetandthePDiscleared.
Otherwise the TO and PD flags remain unchanged.
HT48R50A-1
32
December 19, 2000
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