參數(shù)資料
型號(hào)： HT48R50A-1
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器，用于多I/O接口設(shè)備)
中文描述： 8位高性能RISC架構(gòu)微控制器等的多個(gè)I / O應(yīng)用（高性能，指令類似的RISC的8位微控制器，用于多予適用/輸出接口設(shè)備）
文件頁(yè)數(shù)： 25/50頁(yè)
文件大?。?/td> 345K
代理商： HT48R50A-1
HT48R50A-1
25
December 19, 2000
PROM programming and verification
The
microcontroller is arranged into a 4096 15 bits
program memory and a 16 8 bits option mem-
ory. The program code and option code are
stored in the program and option memories.
The programming of memories can be summa-
rized in nine steps as described below:
program
memory
used
in
the
Power on (V
DD
=6.25V)
Set VPP (RES) to 12.5V
Set CS (PA5) to low
Let PA3~PA0 (AD3~AD0) be the address and
data bus and the PA4 (CLK) be the clock input.
The data on the AD3~AD0 pins will be clocked
into or out of the microcontroller on the falling
edge of PA4 (CLK) for OTP programming and
verification.
The address data contains the code address (12
bits) and two option bits. Acomplete write cycle
will contain four CLK cycles. The first cycle,
bits 0~3 of the address are latched into the de-
vice. The second and third cycles, bits 4~7 and
bits 8~11 are latched respectively. The fourth
cycle,bit2istheTSELoptionbitandbit3isthe
OSEL option bit. Bits 2~3 in the third cycle and
bits 0~1 in the fourth cycle are undefined. If the
TSEL is "1" and the OSEL is "0", the TEST
memory will be read. If the TSEL is "0" and the
OSEL is "1", the option memory will be ac-
cessed. If both the TSEL and OSEL are "0", the
program memory will be managed.
The code data is 15 bits wide. A complete
read/write cycle contains four CLK cycles. In
the first cycle, bits 0~3 of the code data are ac-
cessed. In the second and third, bits 4~7 and
bits 8~11 are accessed respectively. In the
fourth cycle, bits 12~14 are accessed. Bits 15
are undefined. During code verification, read-
ing will return the result "0".
Select the TSEL and OSEL to program and
verify the program memory and option mem-
ory. Use the R/W (PA6) to select between pro-
gramming or verification.
The address is incremented by one automati-
cally after a code verification cycle. If the dis-
continued
address
verification is accomplished, the automatic ad-
dressing increment is disabled. For the discon-
tinued address programming and verification,
the CS pin must return to high level for a pro-
gramming or verification cycle, that is, if a dis-
continued
address
programming or verification cycle must be in-
terrupted and restarted as well.
programming
or
is
managed,
the
The related pins of OTPprogramming and veri-
fication are listed in the following table.
Pin
Name
Function
Description
PA0
AD0
Bit0ofaddress/databus
PA1
AD1
Bit1ofaddress/databus
PA2
AD2
Bit2ofaddress/databus
PA3
AD3
Bit3ofaddress/databus
PA4
CLK
Serial clock input for ad-
dress and data
PA5
CS
Chip select, active low
PA6
R/W
Read/write control input
RES
VPP
Programming the power
supply
The timing charts of programming and verifica-
tion are as shown. There is a LOCK signal for
code protection. If the LOCK is "1", reading the
code will return the result "1". However, if the
LOCK is "0", the code protection is disabled and
the code can be read always until the LOCK is
programmed as "1".
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