HT48R30A-1
Rev. 1.10
13
July 2, 2001
icated RC oscillator (WDT oscillator), RTC
clock or instruction clock (system clock divided
by 4), determines the ROM code option. This
timer is designed to prevent a software mal-
function or sequence from jumping to an un-
known location with unpredictable results. The
Watchdog Timer can be disabled by ROM code
option. If the Watchdog Timer is disabled, all
the executions related to the WDT result in no
operation. The RTC clock is enabled only in the
internal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator
withaperiodof72 s/5Vnormally)isselected,it
is first divided by 256 (8-stage) to get the nomi-
nal time-out period of 18.6ms/5V. This time-out
period may vary with temperatures, VDD and
process variations. By invoking the WDT
prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0
of the WDTS) can give different time-out periods.
IfWS2,WS1,andWS0areallequalto1,thedivi-
sion ratio is up to 1:128, and the maximum
time-outperiodis2.4s/5Vseconds.IftheWDTos-
cillator is disabled, the WDT clock may still come
from the instruction clock and operates in the
same manner except that in the HALT state the
WDT may stop counting and lose its protecting
purpose. In this situation the logic can only be re-
started by external logic. The high nibble and bit
3 of the WDTS are reserved for user's defined
flags, which can be used to indicate some speci-
fied status.
If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) or
32kHz crystal oscillator (RTC OSC) is strongly
recommended, since the HALT will stop the sys-
tem clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will
initialize "chip reset" and set the status bit
"TO". But in the HALT mode, the overflow will
initialize a warm reset and only the PC and
SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level
to RES), software instruction and a "HALT" in-
struction. The software instruction include
"CLR WDT" and the other set
and"CLRWDT2".Ofthesetwotypesofinstruc-
tion, only one can be active depending on the
ROM code option
"CLR WDT times selection
option". If the "CLR WDT" is selected (i.e.
CLRWDT times equal one), any execution of
the "CLR WDT" instruction will clear the WDT.
In the case that "CLR WDT1" and "CLR WDT2"
are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
"CLR WDT1"
Power down operation
HALT
The HALT mode is initialized by the "HALT"
instruction and results in the following...
The system oscillator will be turned off but
the WDT oscillator remains running (if the
WDT oscillator is selected).
The contents of the on chip RAM and regis-
ters remain unchanged.
WDT and WDT prescaler will be cleared and
recounted again (if the WDT clock is from the
WDT oscillator).
All of the I/O ports maintain their original sta-
tus.
The PD flag is set and the TO flag is cleared.
ThesystemcanleavetheHALTmodebymeans
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm re-
set". After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executingthe"CLRWDT"instructionandisset
when executing the "HALT" instruction. The
TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the PC and