參數(shù)資料
型號(hào): HT48R30A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個(gè)I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 8/47頁
文件大小: 306K
代理商: HT48R30A-1
HT48R30A-1
8
November 29, 2000
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table
word are transferred to the lower portion of
TBLH, and the remaining 2-bits words are
read as "0". The Table Higher-order byte reg-
ister (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which
indicates the table location. Before accessing
the table, the location must be placed in the
TBLP. The TBLH is read only and cannot be
restored. If the main routine and the ISR (In-
terrupt Service Routine) both employ the ta-
ble read instruction, the contents of the
TBLH in the main routine are likely to be
changed by the table read instruction used in
the ISR. Errors can occur. In other words, us-
ing the table read instruction in the main rou-
tine and the ISR simultaneously should be
avoided. However, if the table read instruc-
tionhastobeappliedinboththemainroutine
and the ISR, the interrupt is supposed to be
disabled prior to the table read instruction. It
will not be enabled until the TBLH has been
backed up. All table related instructions re-
quire two cycles to complete the operation.
These areas may function as normal program
memory depending upon the requirements.
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter (PC) only. The stack is organized into 4 lev-
els and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledge signal, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledge signal will be in-
hibited. When the stack pointer is (by RET or
RETI), the interrupt will be serviced. This fea-
ture prevents stack overflow allowing the pro-
grammer to use the structure more easily. In a
similar case, if the stack is full and a "CALL" is
subsequently executed, stack overflow occurs
and the first entry will be lost (only the most re-
cent 4 return addresses are stored).
Data memory
RAM
The data memory is designed with 115 8 bits.
The data memory is divided into two func-
tional groups: special function registers and
general purpose data memory (96 8). Most are
read/write, but some are read only.
The special function registers include the indi-
rect
addressing
registers
timer/event counter (TMR;0DH), timer/event
counter control register (TMRC;0EH), pro-
gram counter lower-order byte register
(PCL;06H), memory pointer registers
(MP;01H), accumulator (ACC;05H), table
pointer (TBLP;07H), table higher-order byte
register (TBLH;08H), status register
(STATUS;0AH), interrupt control register
(R0;00H),
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