參數(shù)資料
型號: HT48R30A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個I / O應用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 10/47頁
文件大?。?/td> 306K
代理商: HT48R30A-1
HT48R30A-1
10
November 29, 2000
Status register
STATUS
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD), and
watchdog time-out flag (TO). It also records the
status information and controls the operation
sequence.
With the exception of the TO and PD flags,
bits in the status register can be altered by
instructions like most other registers. Any
data written into the status register will not
change the TO or PD flag. In addition opera-
tions related to the status register may give
different results from those intended. The
TO flag can be affected only by system
power-up, a WDT time-out or executing the
"CLR WDT" or "HALT" instruction. The PD
flag can be affected only by executing the
"HALT" or "CLR WDT" instruction or during
a system power-up.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
In addition, on entering the interrupt sequence
or executing the subroutine call, the status reg-
ister will not be pushed onto the stack automat-
ically. If the contents of the status are
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt and
internal timer/event counter interrupts. The
Interrupt Control Register (INTC;0BH) con-
tains the interrupt control bits to set the en-
able/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any fur-
ther interrupt nesting. Other interrupt re-
quests may occur during this interval but only
the interrupt request flag is recorded. If a cer-
taininterruptrequiresservicingwithintheser-
vice routine, the EMI bit and the corresponding
bit of the INTC may be set to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupts have a wake-up ca-
pability. As an interrupt is serviced, a control
Labels
Bits
Function
C
0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifabor-
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionorno
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by system power-up or executing the "CLR WDT" instruction. PD
is set by executing the "HALT" instruction.
TO
5
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in-
struction. TO is set by a WDT time-out.
6
Undefined, read as "0"
7
Undefined, read as "0"
Status register
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