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參數(shù)資料
| 型號： | HT48CA1 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Remote Type 8-Bit MCU |
| 中文描述： | 遠程型8位微控制器 |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 308K |
| 代理商： | HT48CA1 |
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HT48RA1/HT48CA1
Rev. 1.00
11
June 25, 2004
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 90 s@3V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 23ms@3V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.9s@3V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user s defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS Register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO . But in the HALT
mode, the overflow will initialize a warm reset and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted;externalreset(alowleveltoRES),softwarein-
structionanda HALT instruction.Thesoftwareinstruc-
tion include CLR WDT and the other set CLR WDT1
and CLR WDT2 . Of these two types of instruction,
only one can be active depending on the ROM code op-
tion CLR WDT times selection option. If the CLR
WDT is selected (i.e. CLR WDT times equal one),
any execution of the CLR WDT instruction will clear
the WDT. In the case that
CLR WDT1
and
CLR
WDT2 are chosen (i.e. CLR WDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDTmay reset the chip as a result
of time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDToverflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
thePCandSP;theothersremainintheiroriginalstatus.
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Watchdog Timer
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