參數(shù)資料
型號(hào)： HT46R65-52
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 22/48頁(yè)
文件大?。?/td> 409K
代理商： HT46R65-52
HT46R65/HT46C65
Rev. 1.80
22
July 14, 2005
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
Modulation cycle i
(i=0~1)
i<AC
DC+1
128
i AC
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
PWM
Cycle
Frequency
PWM
Cycle
Duty
f
SYS
/64 for (6+2) bits mode
f
SYS
/128 for (7+1) bits mode
f
SYS
/256
[PWM]/256
A/D Converter
The 8 channels and 10 bits resolution A/D converter are
implemented in this microcontroller. The reference volt-
age is VDD. The A/D converter contains 4 special regis-
ters which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control regis-
ter, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the con-
verted analog channel, and give STARTbit a rising edge
and falling edge (0
sion, the EOCB bit is cleared. The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
1
0). At the end of A/D conver-
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is powered-on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure that the A/D conversion is completed,
the START should remain at
0
until the EOCB is
cleared to 0 (end of A/D conversion).
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to 1
when the START bit is set from 0 to 1 .
Important Note for A/D initialization:
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
Bit No.
Label
Function
0
1
ADCS0
ADCS1
Selects the A/D converter clock
source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
2~6
Unused bit, read as 0
7
TEST
For test mode used only
ACSR (27H) Register
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