HT46R65/HT46C65
Rev. 1.80
15
July 14, 2005
Reset
There are three ways in which reset may occur.
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the initial condition once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
chip resets .
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC,
Time Base
Cleared. After master reset,
WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
' '
'
' D
/ E
' D '
/ E
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
)
7
%
) )
>
Reset Timing Chart
(
9 " $
(
7
=
1
1
A
7
)
' 7 @
)
1
(
)
Reset Configuration