HT46R64/HT46C64
Rev. 1.40
18
September 21, 2004
Label
(TMR1C)
Bits
Function
0~2
Unused bit, read as 0
T1E
3
Defines the TMR1 active edge of the timer/event counter
(0= active on low to high; 1= active on high to low)
T1ON
4
Enable/disable timer counting
(0= disabled; 1= enabled)
T1S
5
Defines the TMR1 internal clock source
(0=f
SYS
/4; 1=32768Hz)
T1M0
T1M1
6
7
Defines the operating mode T1M1, T1M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C Register
In the event count or timer mode, the timer/event coun-
ter 0(1) starts counting at the current contents in the
timer/event counter 0(1) and ends at FFH(FFFFH).
Once an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and generates
an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4
of INTC1). In the pulse width measurement mode with
the values of the T0ON/T1ON and T0E/T1E bits equal
to 1, after the TMR0 (TMR1) has received a transient
from low to high (or high to low if the TE bit is 0 ), it will
start counting until the TMR0 (TMR1) returns to the orig-
inal level and resets the T0ON/T1ON. The measured re-
sult remains in the timer/event counter even if the
activated transient occurs again. In other words, only
1-cycle measurement can be made until the
T0ON/T1ON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting not according to the logic level but to the tran-
sient edges. In the case of counter overflows, the coun-
ter is reloaded from the timer/event counter register and
issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON/T1ON is automatically cleared after the measure-
ment cycle is completed. But in the other two modes, the
T0ON/T1ON can only be reset by instructions. The
overflow of the Timer/Event Counter 0/1 is one of the
wake-upsourcesandcanalsobeappliedtoaPFD(Pro-
grammable Frequency Divider) output at PA3 by op-
Label
(TMR0C)
Bits
Function
T0PSC0
T0PSC1
T0PSC2
0
1
2
To define the prescaler stages.
T0PSC2, T0PSC1, T0PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
T0E
3
Defines the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
T0ON
4
Enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
T0M0
T0M1
6
7
Defines the operating mode T0M1, T0M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR0C Register