參數資料
型號: HT46C47
廠商: Holtek Semiconductor Inc.
英文描述: Cost-Effective A/D Type 8-Bit MCU
中文描述: 成本效益的A / D型8位微控制器
文件頁數: 15/42頁
文件大小: 291K
代理商: HT46C47
HT46R46/HT46C46/HT46R47/HT46C47
Rev. 1.00
15
December 28, 2004
Bit No.
Label
Function
0
1
2
PSC0
PSC1
PSC2
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
Enable or disable the timer counting
(0=disable; 1=enable)
5
Unused bits, read as 0
6
7
TM0
TM1
Defines the operating mode (TM1, TM0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
come from an external source or the system clock.
Usingexternalclockinputallowstheusertocountexter-
nal events, measure time internals or pulse widths, or
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time
base.
The timer/event counter can generate PFD signal by us-
ing external or internal clock and PFD frequency is de-
termine by the equation f
INT
/[2 (256-N)].
There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer/event counter preload
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter
control register, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the f
INT
clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the f
INT
.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt re-
quest flag (TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR has received a
transient from low to high (or high to low if the TE bits is
0 ) it will start counting until the TMR returns to the orig-
inal level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared au-
tomatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
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