參數(shù)資料
型號(hào)： HT36A1
廠商： Holtek Semiconductor Inc.
英文描述： Music Synthesizer 8-Bit MCU
中文描述： 音樂(lè)合成器8位微控制器
文件頁(yè)數(shù)： 11/39頁(yè)
文件大?。?/td> 286K
代理商： HT36A1
HT36A1
Rev. 1.00
11
August 15, 2005
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscilla-
tion may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystalacrossOSC1andOSC2isneededtoprovidethe
feedback and phase shift required for the oscillator, and
no other external components are required. Aresonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDToscillator still works with a
period of approximately 78 s. The WDT oscillator can
be disabled by mask option to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown loca-
tionwithunpredictableresults.TheWatchdogTimercan
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 78 s normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of ap-
proximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALTstate the WDTmay stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a warm reset
only the program counter and SP are reset to zero. To
clear the WDT contents (including the WDT prescaler ),
3 methods are implemented; external reset (a low level
to RES), software instructions, or a HALT instruction.
The software instructions include CLR WDT and the
other set
types of instructions, only one can be active depending
CLR WDT1 and CLR WDT2. Of these two
on the mask option
CLR WDT times selection op-
tion . If the CLR WDT is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction
will clear the WDT. In case CLR WDT1 and CLR
WDT2
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip because
of time-out.
are chosen (i.e. CLRWDT times equal two),
Power Down Operation
HALT
The HALT mode is initialized by a HALT instruction and
results in the following...
The system oscillator will turn off but the WDT oscilla-
tor keeps running (If the WDT oscillator is selected).
Watchdog Timer
WDT
! 2
: )
; 1 4
)
;
C
# 6 )
1
)
;
;
)
E
C
# 6 ) 6 :
;
C
!
C
!
4
;
!
1
C
# 6
!
Watchdog Timer
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