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參數(shù)資料
| 型號： | HT24LC08 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 160K |
| 代理商： | HT24LC08 |
HT24LC08
Rev. 1.30
4
November 25, 2003
These page addressing bits on the 8K device should be
considered the most significant bits of the data word ad-
dress which follows. The A0, A1 and A2 pins have no
connection.
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Write Operations
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
Page write
The 8K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop con-
dition after the first data word is clocked in. Instead, af-
ter the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
zero after each data word received. The
microcontrollermustterminatethepagewritesequence
with a stop condition (refer to Page write timing).
Thedatawordaddresslowerfourbitsareinternallyin-
cremented following the receipt of each data word.
The higher data word address bits are not incre-
mented, retaining the memory page row location.
Acknowledge polling
To maximize bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
Write protect
The HT24LC08 has a write-protect function and pro-
gramming will then be inhibited when the WP pin is
connectedtoVCC.Underthismode,theHT24LC08is
used as a serial ROM.
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Byte Write Timing
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Page Write Timing
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Acknowledge Polling Flow
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