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參數(shù)資料
| 型號(hào)： | HT24LC04 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 4K-Bit 2-Wire Serial Interface CMOS Serial EEPROM(4K位、2線接口、 CMOS串行EEPROM) |
| 中文描述： | 4K的位2線串行接口的CMOS串行EEPROM（4K的位，2線接口，串行EEPROM中的CMOS） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 228K |
| 代理商： | HT24LC04 |
Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock
data into each E E PROM device and negative
edge clock data out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data
transfer. The pin is open-drain driven and
may be wired-OR with any number of other
open-drain or open collector devices.
A0, A1, A2
The HT24LC04 uses the A2 and A1 inputs for
hard wire addressing and a total of four 4K
devices may be addressed on a single bus
system. The A0 pin is not connected. (The
device addressing is discussed in detail under
the Device Addressing section).
Write protect (WP)
The HT24LC04 has a write protect pin that
provides hardware data protection. The write
protect pin allows normal read/write opera-
tions when connected to the V
SS
. When the
write protect pin is connected to Vcc, the write
protection feature is enabled and operates as
shown in the following table.
WP Pin
Status
Protect Array
HT 24L C04
Full Array (4K )
At V
CC
At V
SS
Normal Read/Write Operations
Memory organization
HT24LC04, 4K Serial E E PROM
Internally organized with 512 8-bit words,
random word addressing requires a 9-bit data
word address.
Device operations
Clock and data transition
Data transfer may be initiated only when the
bus is not busy. During data transfer, the data
line must remain stable whenever the clock
line is high. Changes in data line while the
clock line is high will be interpreted as a
START or STOP condition.
Start condition
A high-to-low transition of SDA with SCL high
is a start condition which must precede any
other command (refer to Start and Stop Defi-
nition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL high
is a stop condition. After a read sequence, the
stop command will place the E E PROM in a
standby power mode (refer to Start and Stop
Definition Timing Diagram).
Acknowledge
All addresses and data words are serially
transmitted to and from the E E PROM in 8-bit
words. The E E PROM sends a zero to acknow-
ledge that it has received each word. This
happens during the ninth clock cycle.
Device addressing
The 4K E E PROM devices require an 8-bit de-
vice address word following a start condition to
enable the chip for a read or write operation.
The device address word consist of a mandatory
one, zero sequence for the first four most signifi-
cant bits (refer to diagram showing the Device
Address). This is common to all the E E PROM
device.
The next three bits are the A2, A1 and A0 device
address bits for the 1K /2K E E PROM. These
three bits must compare to their corresponding
hard-wired input pins.
HT24LC04
4
6th May ’99
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT24LC04(8DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC04(8SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC04_10 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 4K 2-Wire Serial EEPROM |
| HT24LC04-8DIP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC04-8SOP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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