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參數(shù)資料
| 型號(hào)： | HT24LC01 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 1K/2K 2-Wire CMOS Serial EEPROM |
| 中文描述： | 1K/2K 2線的CMOS串行EEPROM |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 248K |
| 代理商： | HT24LC01 |
The 8th bit of device address is the read/write
operation select bit. A read operation is initi-
ated if this bit is high and a write operation is
initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the
chip will return to a standby state.
Write operations
Byte write
A write operation requires an 8-bit data word
address following the device address word
and acknowledgment. Upon receipt of this ad-
dress, the E E PROM will again respond with a
zero and then clock in the first 8-bit data
word. After receiving the 8-bit data word, the
E E PROM will output a zero and the address-
ing device, such as a microcontroller, must
terminate the write sequence with a stop con-
dition. At this time the E E PROM enters an
internally-timed write cycle to the non-vola-
tile memory. All inputs are disabled during
this write cycle and E E PROM will not re-
spond until the write is completed (refer to
Byte write timing).
Page write
The 1K /2K EEPROM is capable of an 8-byte
page write.
A page write is initiated the same as byte
write, but the microcontroller does not send a
stop condition after the first data word is
clocked in. Instead, after the E E PROM ac-
knowledges the receipt of the first data word,
the microcontroller can transmit up to seven
more data words. The E E PROM will respond
with a zero after each data word received. The
microcontroller must terminate the page
write sequence with a stop condition.
The data word address lower three (1K /2K )
bits are internally incremented following the
receipt of each data word. The higher data
word address bits are not incremented, re-
taining the memory page row location (refer
to Page write timing).
Acknowledge polling
Since the device will not acknowledge during
a write cycle, this can be used to determine
when the cycle is complete (this feature can be
used to maximize bus throughput). Once the
stop condition for a write command has been
issued from the master, the device initiates
the internally timed write cycle. ACK polling
can be initiated immediately. This involves
the master sending a start condition followed
by the control byte for a write command
(R/W=0). If the device is still busy with the
HT24LC01/02
5
6th May ’99
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT24LC02 | 2K-Bit 2-Wire Serial Interface CMOS Serial EEPROM(2K位、2線接口、 CMOS串行EEPROM) |
| HT24LC04 | 4K-Bit 2-Wire Serial Interface CMOS Serial EEPROM(4K位、2線接口、 CMOS串行EEPROM) |
| HT24LC08 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| HT24LC16 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| HT25LC512 | CMOS 64Kx8-Bit SPI Serial OTP EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT24LC02 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:1K/2K 2-Wire CMOS Serial EEPROM |
| HT24LC02(8DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(8SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(8TSSOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(SOP) | 制造商:Holtek Semiconductor Inc 功能描述:CMOS 2K 2-WIRE SERIAL EEPROM, SO8 |
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