參數(shù)資料
型號: HT23B60-100QFP-A
廠商: Holtek Semiconductor Inc.
英文描述: 60x11 Pixel Data Bank 8-Bit Mask MCU
中文描述: 60x11像素數(shù)據(jù)銀行8位微控制器面膜
文件頁數(shù): 8/50頁
文件大?。?/td> 314K
代理商: HT23B60-100QFP-A
HT23B60
Rev. 1.10
8
March 1, 2004
Functional Description
Execution Flow
The system clock for the HT23B60 is derived from a
32768Hz crystal oscillator. A built-in frequency up con-
version circuit provides dual system clock, namely
32768Hz and 3.58MHz. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
Program Counter
PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by 1. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
'
(
)
"
'
(
)
"
'
(
)
"
4
-
- >
6 @
-
- >
A '
4
-
>
B '
6 @
-
>
4
-
- >
B (
6 @
-
- >
B '
B '
B (
-
/
0
( - >
-
/
3
0 &
3
0 '
3
0 (
* ' = (
' $
- - - 3
& & & & +
' 4 4 4 +
0
3
0 -
3
$ 9 3
# -
-
' " 9
' ) -
- 3
-
-
- 6 @
- - C
-
-
/ / -
) ( ! -
-
-
-
' ) - 7
( & & & +
) 4 4 4 +
" & & & +
# 4 4 4 + -
3
0 )
$ & & & +
% 4 4 4 + -
Execution Flow
Mode
Program ROM Address
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External or Serial Input
Interrupt
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
TimerCounter0Overflow
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
TimerCounter2Overflow
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Keyscan Overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
RTC Overflow
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
PWM Interrupt
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
PC+2
Loading PCL
*14
*13
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
BP.6 BP.5 #12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S14 S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program ROM Address
Note: *14~*0: Program ROM address
S14~S0: Stack register bits
@7~@0: PCL bits
BP.5, BP.6: Bit 5, 6 of bank pointer (04H)
#12~#0: Instruction code bits
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