
HT23B60
Rev. 1.10
17
March 1, 2004
Register
Label
Bit No.
Function
INTC1
(1EH)
EKSI
0
Controls the keyscan interrupt. (1=enable; 0=disable)
ERTCI
1
Controls the RTC interrupt. (1=enable; 0=disable)
EPWMI
2
PWM D/A interrupt (1=enable; 0=disable)
3
Should be set 0 always.
KSF
4
Keyscan interrupt request flag. (1=active; 0=inactive)
RTCF
5
RTC interrupt request flag. (1=active; 0=inactive)
PWMF
6
PWM D/A flag (1=enable; 0=disable)
7
Should be set 0 always.
INTCH register
Oscillator Configuration
There are two oscillator circuits in the controller, the ex-
ternal 32768Hz crystal oscillator and internal WDT RC
oscillator.
The 32768Hz crystal oscillator and frequency-up con-
version circuit (32768Hz to 3.58MHz) are designed for
dual system clock source. It is necessary for the fre-
quency conversion circuit to add external RC compo-
nents to make up the low pass filter that stabilize the
output frequency 3.58MHz (see the oscillator circuit).
The WDT RC oscillator is a free running on-chip RC os-
cillator, and no external components are required. Even
if the system enters the Idle mode (the system clock is
stopped), the WDT RC oscillator still works within a pe-
riod of 65 s~78 s. When the WDT is disabled or the
WDT source is not this RC oscillator, the WDT RC
oscillator will be disabled.
Watchdog Timer
WDT
The WDT clock source is implemented by a WDT OSC
or external 32768Hz or an instruction clock (system
clock divided by 4), determined by mask option. This
timer is designed to prevent software malfunction or
protect the sequence from jumping to an unknown loca-
tion with unpredictable results. The Watchdog Timer
can be disabled by mask option. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDTclock source is selected, it will be first di-
vided by 512 (9-stage) to get the nominal time-out pe-
riod. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is 78 s. This time-out period may
varywithtemperature,VDDandprocessvariations.The
WDT OSC always works for any operation mode.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except
in the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
Register
Label
Bits
R/W
Function
WDTS
(09H)
WS0
WS1
WS2
0
1
2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
7~3
RW
Unused bit. These bits are read/write-able.
'
(
' # 0
)
4
# &
4
) ( % $ *
System Oscillator Circuit