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參數(shù)資料
| 型號： | HSP50307SC |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Burst QPSK Modulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 48K |
| 代理商： | HSP50307SC |
7-72
Applications Example
Figure 4 shows an applications example of the HSP50307.
The MCLK source operates at 25.6MHz, and the RCLK
operates at 2.048MHz. 0.1
μ
F capacitors are connected from
the IBBOUT to IBBIN and the QBBOUT to QBBIN, providing
AC coupling to the Analog Upconverter Section of the
HSP50307.
The control processor sends the 23-bit control word via the
three-wire interface. The data source receives the 256kHz
TXCLK from the HSP50307 and transmits data and enable
signal at the 256kHz rate.
The DAC_REF and VCM_REF are connected to 0.1
μ
F
capacitors to ground. Each of the differential drivers are
loaded with a 37.5
resistor and a 0.1
μ
F capacitor. The
37.5
resistors provide matching to the 75
cable. The
capacitors perform AC coupling. The drive paths are sent to
the cable transformer for data transmissions.
Table 3 shows the general functional specifications for the
applications example shown in Figure 4. It gives an overview
of what is being accomplished but does not specify an exact
carrier frequency or other programmable functions. These
specifications are met given a valid control word combination
and the applications circuit shown in Figure 4. Table 4 sum-
marizes the performance of the applications example shown
in Figure 4. Again, these specifications are met given a valid
programmed mode.
NOTE: The HSP50307 is sensitive to layout. Users must
make sure the input signals do not couple back into the
output signals. The performance of the HSP50307 is
also sensitive to the decoupling capacitors between
1) QBBOUT and QBBIN and 2) IBBOUT and IBBIN. The
values shown in Figure 4 are recommended
.
0.1
μ
F
CCLK
C_EN
DVCC
RCLK
AGND
VCO_IN
AVCC
MOD_OUT-
MOD_OUT+
AVDD
AGND
CDATA
PD_OUT
VCO_SET
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLK
TX_EN
TX_DATA
RESET
DGND
AGND
QBBOUT
QBBIN
IBBIN
DAC_REF
VCM_REF
TXCLK
AVCC
IBBOUT
0.1
μ
F
0.1
μ
F
0.1
μ
F
+5V
ANALOG
0.1
μ
F
DGND
AGND
25.6MHz
OSC
DATA
SOURCE
0.1
μ
F
DGND
CONTROL
PROC.
2.048MHz
OSC
0.01
μ
F
2k
6.25k
100pF
0.01
μ
F
+5V
ANALOG
37.5
0.1
μ
F
CABLE
TRANSFORMER
37.5
0.1
μ
F
0.1
μ
F
+9V
ANALOG
+5V
DIGITAL
AGND
FIGURE 4. APPLICATIONS EXAMPLE OF THE HSP50307
RFOUT
HSP50307
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