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參數(shù)資料
| 型號(hào)： | HSP50307SC |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Burst QPSK Modulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 48K |
| 代理商： | HSP50307SC |
7-70
Functional Description
The HSP50307 is designed to transmit 256 KBPS data
using QPSK modulation on a programmable carrier over
75
cable lines. The incoming 256 KBPS data is first
demultiplexed into in-phase (I) and quadrature (Q) data
streams. The burst QPSK modulator shapes the two
128 KBPS demultiplexed data streams using interpolate-
by-8 root-raised cosine (RRC) filters with
α
= 0.5. The
resulting 1.024MHz data streams are sent through D/A
converters
and
are
then
reconstruction filters for over 40dB image rejection. The
baseband analog output and input pins allow the signals to
be AC coupled. The returning analog signal is upconverted
by an analog quadrature modulator. The control section is
configured by loading 23 bits of information via a three-wire
interface. These bits configure the DSP filter section, the
carrier frequency, the analog synthesizer, and the output
driver sections.
sent
through
low-pass
Digital Filters
The burst QPSK modulator uses an interpolate-by-8 digital
RRC filter on both the I and Q data streams. The shaping
factor is set to
α
= 0.5. The FIR order of the digital RRC filter
is 64. Figure 1 shows the impulse response of the RRC filter.
Figure 2 is a spectrum analyzer plot of the modulator output
for a baud rate of 128 kbaud and a pseudorandom data pat-
tern. The 128kHz 3dB bandwidth and 192kHz stopband
edges are readily apparent.
AVCC
I
Positive supply for the synthesizer (+5V analog). (P)
VCO_SET
I/O
VCO free running frequency set resistor (normally 6.25k
). (D)
VCO_IN
I
Voltage-controlled oscillator control voltage. (D)
PD_OUT
O
Phase/frequency detector output. (D)
AGND
I
Negative supply for the synthesizer. (P)
RCLK
I
Synthesizer reference clock input (2.048MHz). (D)
DVCC
I
Positive supply for the digital filters and control (+5V digital). (P)
C_EN
I
Control interface enable for 3 wire interface. See Control Interface Section. (D)
CDATA
I
Serial data input for 3 wire interface. See Control Interface Section. (D)
CCLK
I
3 wire interface clock. See Control Interface Section. (D)
NOTE: (A) = analog, (D) = digital, (P) = power.
Pin Description
(Continued)
SYMBOL
TYPE
DESCRIPTION
FIGURE 1. NORMALIZED IMPULSE RESPONSE OF THE RRC
INTERPOLATION FILTER WITH
α
= 0.5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
1
-0.2
8
16
24
32
40
48
56
64
TAP NUMBER
C
FIGURE 2. SPECTRUM OF 8.096MHz RANDOM DATA MODU-
LATED CARRIER
REF -15.0 dBm
PEAK
LOG
5dB/
WA SB
SC FS
CORR
CENTER 8.0960MHz
#RES BW 300Hz
VBW 300Hz
SPAN 400.0kHz
SWP 13.3s
# AT 60dB
MKR 8.0960MHz
-16.83dBm
HSP50307
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