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參數(shù)資料
| 型號： | HSP50214 |
| 廠商： | Intersil Corporation |
| 英文描述： | Programmable Downconverter |
| 中文描述： | 可編程變頻器 |
| 文件頁數(shù)： | 50/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214 |
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50
CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
AGC Load
Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to
the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator
with bits (15:12) mapping to the shift (exponent) control bits and bits (11:5) mapping to the mul-
tiplier (mantissa) bits. Bits (11:5) represent a binary mantissa mapped to the linear gain as:
01.XXXXXXX. See AGC Section.
CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
31-0
Reserved
A fixed value 0000 0010 0111 1000 [0278]
HEX
is loaded here for normal operation. A fixed value
0000 0010 0111 1010 [027A]
HEX
is loaded here for setting the Sin/Cos generator outputs to
7FFF.
CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-10
Discriminator FIR
Coefficient
The discriminator FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the co-
efficients are loaded from the center coefficient at address 64 to the last coefficient. If the filter
is asymmetric the coefficients C
0
to C
N
are loaded with C
0
in address 64 up to 64+N, where N
is number of asymmetric coefficients.
CONTROL WORDS 128-255: 255 PROGRAMMABLE COEFFICIENT REGISTERS
BIT
POSITION
FUNCTION
DESCRIPTION
31-10
Programmable FIR
Coefficient
The programmable FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the
coefficients are loaded from the center coefficient at address 128 to the last coefficient. If the
filter is asymmetric the coefficients C
0
to C
N
are loaded with C
0
in address 128 up to 128+N,
where N is number of asymmetric coefficients.
Real Filters are computed as:
Xn-k+1 Ck1 + Xn-k+2 Ck-2 + ... XnC0).
where C0 is the coefficient in address 128 and Xo is the oldest data sample.
Complex filters outputs are computed as follows:
Xn is the most recent data sample.
k is the number of samples = number of (complex) taps.
C0_re is the coefficient loaded into CW128.
C0_im is the coefficient loaded into CW129.
The convolution starts with the oldest data, times the last complex coefficient, and ends with
the newest data, times the first complex coefficient loaded.
Iout
= (-Xn-k+1_q * Ck-1_im + Xn-k+1_i * Ck-1_re).
+ (-Xn-k+2_q * Ck-2_im + Xn-1+2_i * Ck-2_re).
+ ...
+ (-Xn_q * C0_im + Xn_i * C0_re).
Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re).
+ (Xn-k+2_i * Ck-2_im + Xn-1+2_q * Ck-2_re).
+ ...
+ (Xn_i * C0_im + Xn_q * C0_re).
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
| HSP50216 | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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