- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385396 > HSP50214 (Intersil Corporation) Programmable Downconverter PDF資料下載
參數(shù)資料
| 型號： | HSP50214 |
| 廠商： | Intersil Corporation |
| 英文描述： | Programmable Downconverter |
| 中文描述： | 可編程變頻器 |
| 文件頁數(shù)： | 34/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
34
FIFO Operation via 8-Bit
μ
Processor
Interface
The Buffer RAM Output may also be accessed via the 8-bit
microprocessor interface C(7:0). Figure 39 shows the con-
ceptual configuration of the 8-bit
μ
processor interface. Con-
trol Word 20 bit 24 must be set to 0 in order to obtain Buffer
RAM data to this output. The Microprocessor Read section
describes how to read the data from each sample out of the
C(7:0) interface.
Recall that INTRRP stays low for 8 PROCCLK cycles. The
FIFO can be read before the INTRRP signal goes low; the
number of samples in the FIFO must be monitored by the user.
Figure 38 illustrates the timing for RAM load sequence.
The read pointer of the FIFO is incremented when Control
Word 23 is written to. The data can not be read from the
next sample until 4 PROCCLKs after the Buffer RAM
pointer has been incremented. Control Word 22 is used to
reset the Read and Write pointers of the Buffer RAM output
to the first sample to 000 and 007 for write and read
respectively.
FIGURE 38. RAM LOAD SEQUENCE
PROCCLK
DATARDY
(I/Q SELECTED)
DATARDY
(R/
φ
SELECTED)
INTRPT
WRITES TO
SNAPSHOT
RAM
I/Q
R/
φ
I
Q
R
φ
DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN
TIMING
|r|
φ
Q
DUAL
PORT
RAM
16
ADDRESS
SEQUENCER
INCR
WR
“SET OF WORDS”
16
16
16
D
D
16
I
RD
INCR
WRITE
SEQUENCER
|r|
φ
Q
I
STATUS
0
1
2
3
4
NEW
DATA
M
FIGURE 39. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM
OUTPUT
DATA
0
1
0
1
0
1
0
1
WRITE
ADDRESS “5”
CONTROL
WORD 23
R0
R1
R2
A0
A1
R0 A1
LSByte
MSByte
2
3
INT(15:0)
INT(22:16)
AGC
A(2:0)
RD
R2, R1, R0
0: I;Q
1: |r|;
φ
2:
4: INPUT AGC
5: AGC; TIMING
M
M
M
M
M
A2, A1, A0
A1
A2
A0
R2 R1 R0 A2 A1 A0 SELECTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
1
X
X
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
1
1
X
X
X
X
X
X
1
1
0 RAM I LSB
1 RAM I MSB
0 RAM Q LSB
1 RAM Q MSB
0 RAM |r| LSB
1 RAM |r| MSB
0 RAM
φ
LSB
1 RAM
φ
MSB
0 RAM
LSB
1 RAM
MSB
X NOT USED
0 INPUT INTEG LSB
1 INPUT INTEG NMSB
0 INPUT INTEG MSB
0 AGC LSB
1 AGC MSB
0 TIMING LSB
1 TIMING MSB
X NOT USED
1 STATUS
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
| HSP50215 | Digital UpConverter(數(shù)字上變頻器) |
| HSP50216 | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。