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參數(shù)資料
| 型號： | HSP45116A |
| 廠商： | Intersil Corporation |
| 英文描述： | Numerically Controlled Oscillator/ Modulator |
| 中文描述： | 數(shù)控振蕩器/調(diào)制器 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 114K |
| 代理商： | HSP45116A |
3-200
PMSEL
39
I
Phase Modulation Select Line. This line determines the source of the data clocked into the Phase
Register. When high, the Phase Control Register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the least
significant 14 bits are set to zero. This control is registered by CLK.
RBYTILD
30
I
ROM Bypass, Timer Load (active low). Registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16 bit phase adder output and lower 16 bits of the phase accumulator go directly
to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the Timer
Accumulator Register by zeroing the feedback in the accumulator.
PACI
37
I
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one in addition to the values in the Phase Accumulator Register and frequency
adder.
PACO
79
O
Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output indicates
that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has been
reached.
TICO
33
O
Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.
RIN0-18
2-6, 8-19, 21, 23
I
Real Input Data Bus. RIN18 is the MSB. This is the external real component into the complex
multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s
complement.
IMIN0-18
1, 138-142, 144,
146-156, 158
I
Imaginary Input Data Bus. IMIN18 is the MSB. This is the external imaginary component into the
complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is
asserted. Two’s complement.
SH0-1
24, 25
I
Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex
multiplier. The shift controls are common to the shifters on both of the busses.
ACC
26
I
Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled. When
low, the feedback in the accumulators is zeroed to cause the accumulators to load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.
BINFMT
31
I
This input is used to convert the two’s complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.
PEAK
29
I
This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the Output Holding Registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the Holding Registers at the time that PEAK
is activated.
Pin Description
(Continued)
NAME
NUMBER
TYPE
DESCRIPTION
SH1
SH0
SELECTED BITS
0
0
RIN0-15, IMIN0-15
0
1
RIN1-16, IMIN1-16
1
0
RIN2-17, IMIN2-17
1
1
RIN3-18, IMIN3-18
HSP45116A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP45116A_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Numerically Controlled Oscillator/Modulator |
| HSP45116AVC-52 | 功能描述:可編程振蕩器 16 BIT NUMERICALLY CONTROLLER DSC/MDD 16 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45116AVC-52Z | 功能描述:可編程振蕩器 W/ANNEAL 16 BIT CNTRLR DSC/MDD 16 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45116-DB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:HSP45116 Daughter Board |
| HSP45116DB-EVAL | 功能描述:子卡和OEM板 HSP45116 DAUGHTER EV EVAL BRD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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