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參數(shù)資料
| 型號(hào)： | HSP45116A |
| 廠商： | Intersil Corporation |
| 英文描述： | Numerically Controlled Oscillator/ Modulator |
| 中文描述： | 數(shù)控振蕩器/調(diào)制器 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | HSP45116A |
3-199
Pin Description
NAME
NUMBER
TYPE
DESCRIPTION
V
CC
22, 34, 50, 87, 95,
102, 111, 124, 132,
145, 159
-
+5V Power supply input.
GND
7, 20, 32, 48, 62, 73,
83, 92, 98, 108,
114, 119, 125, 131,
143, 157
-
Power supply ground input.
C0-15
54-61, 63-70
I
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
AD0-1
51, 52
I
Address pins for selecting destination of C0-15 data. AD1 is the MSB.
CS
47
I
Chip select (active low).
WR
53
I
Write Enable. Data is clocked into the input register selected by AD0-1 on the rising edge of WR
when the CS line is low.
CLK
49
I
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
ENPHREG
27
I
Phase Register Enable (active low). Registered on chip by CLK. When active low, after being
clocked onto chip, ENPHREG enables the clocking of data into the Phase Register.
ENOFREG
28
I
Frequency Offset Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of frequency offset data into the frequency
offset register.
ENCFREG
42
I
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the Center Frequency Register.
ENPHAC
43
I
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the Phase Accumulator Register.
ENTIREG
44
I
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENTIREG enables clocking of data into the Time Accumulator Register.
ENI
45
I
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
MODPI/2PI
46
I
Modulo
π
/2
π
Select. When low, the Sine and Cosine ROMs are addressed modulo 2
π
(360
degrees). When high, the most significant address bit is held low so that the ROMs are addressed
modulo
π
(180 degrees). This input is registered on chip by clock. This control pin was included
for FFT processing.
CLROFR
41
I
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the Frequency Offset Register
to the frequency adder. New data can still be clocked into the Frequency Offset Register;
CLROFR does not affect the contents of the register.
LOAD
38
I
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the Phase Accumulator Register.
MOD0-1
35, 36
I
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180,
or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase
control path are set to zero.
These bits are loaded into the Phase Register when ENPHREG is low.
MOD1
0
0
1
1
MOD0
0
1
0
1
PHASE SHIFT (DEGREES)
0
90
270
180
HSP45116A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP45116A_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Numerically Controlled Oscillator/Modulator |
| HSP45116AVC-52 | 功能描述:可編程振蕩器 16 BIT NUMERICALLY CONTROLLER DSC/MDD 16 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45116AVC-52Z | 功能描述:可編程振蕩器 W/ANNEAL 16 BIT CNTRLR DSC/MDD 16 RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45116-DB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:HSP45116 Daughter Board |
| HSP45116DB-EVAL | 功能描述:子卡和OEM板 HSP45116 DAUGHTER EV EVAL BRD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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