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參數(shù)資料
| 型號： | HSDL-3210 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | IrDA㈢ Compliant Low Power 1.15 Mbit/s Infrared Transceiver |
| 中文描述： | 紅外㈢符合低功耗1.15 Mbit / s的紅外收發(fā)器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 475K |
| 代理商： | HSDL-3210 |
17
Figure 19. General command format.
STC Bus Protocol and Timing
Diagrams
Bus Protocol
A set of commands is provided to
handle the various transactions
between the master and the slave.
The general format is shown in
Figure 19 whereby communica-
tions consist of a mandatory
command phase followed by an
optional response phase. The
response phase occurs only when
the slave needs to respond to a
command.
The command format consists of
either 2 or 3 bytes command.
The first byte, which is manda-
tory and common to all trans-
actions, consists of the address/
index/control bits. There are two
control fields. The first one is the
“C” field which determines
whether the command is a read
or write operation or to act as a
qualifier for a special operation.
The second one is the “INDX”
field whereby certain patterns
define Special Transactions while
others are for normal Data Trans-
actions. The “ADDR” field is used
to specify which transceiver the
command is for. In a single
transceiver system, this field is
set to “000”.
The second byte contains the
data payload for a 2 byte com-
mand. For a 3 byte command,
this second byte is an 8 bit
extended index.
The third byte is the data payload
when the extended index is used.
ADDR (3)
INDX (4)
C (1)
0
7
1st BYTE
DATA (SLAVE RESPONSE) or E_INDX (8)
0
7
2nd BYTE
DATA (SLAVE RESPONSE) (8)
0
7
3rd BYTE
Figure 20. Write command phase format.
ADDR [2:0]
INDX [3:0]
DATA
ADDR [2:0]
E_INDX[7:0]
1
1
1
1
1
1
DATA
Read Transactions
Read transactions occur when the
master queries the internal regis-
ters of the slave. The initial com-
mand phase is always followed by
the response phase from the
slave as shown below.
ADDR [2:0]
INDX [3:0]
0
ADDR [2:0]
E_INDX[7:0]
1
1
1
1
0
DATA
Figure 21a. Read command phase format.
Figure 21b. Slave response format.
Write Transactions
Write transactions are when the
master writes data to the slave to
select the slave’s operational
mode. This requires only the
command phase as shown below.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSDL-3210-021 | 功能描述:紅外收發(fā)器 20-30cm MIR RoHS:否 制造商:Vishay Semiconductors 波長:900 nm 連續(xù)數(shù)據(jù)傳輸:115.2 Kbit/s 傳輸距離:1 m 輻射強度:60 mW/sr 半強度角度:44 deg 脈沖寬度:2 us 最大上升時間:100 ns 最大下降時間:100 ns LED 電源電壓:- 0.5 V to 6 V 最大正向電流:80 mA 工作電壓:2.4 V to 5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 尺寸:6 mm x 3.1 mm x 1.9 mm 封裝 / 箱體: 封裝:Reel |
| HSDL-3211 | 制造商:AVAGO 制造商全稱:AVAGO TECHNOLOGIES LIMITED 功能描述:IrDA㈢ Data Compliant Low Power 1.15 Mbit/s Infrared Transceiver |
| HSDL-3211-021 | 功能描述:紅外收發(fā)器 Short Distance 3V M IR RoHS:否 制造商:Vishay Semiconductors 波長:900 nm 連續(xù)數(shù)據(jù)傳輸:115.2 Kbit/s 傳輸距離:1 m 輻射強度:60 mW/sr 半強度角度:44 deg 脈沖寬度:2 us 最大上升時間:100 ns 最大下降時間:100 ns LED 電源電壓:- 0.5 V to 6 V 最大正向電流:80 mA 工作電壓:2.4 V to 5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 尺寸:6 mm x 3.1 mm x 1.9 mm 封裝 / 箱體: 封裝:Reel |
| HSDL-3220 | 制造商:Avago Technologies 功能描述:TRANSCEIVER IRDA 4MB/S |
| HSDL-3220-001 | 制造商:AVAGO 制造商全稱:AVAGO TECHNOLOGIES LIMITED 功能描述:IrDA㈢ Data Compliant Low Power 4.0 Mbit/s Infrared Transceiver |
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