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參數(shù)資料
| 型號： | HS9-80C86RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened 16-Bit CMOS Microprocessor |
| 中文描述： | 輻射加固16位CMOS微處理器 |
| 文件頁數(shù)： | 22/37頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HS9-80C86RH |
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877
Spec Number
518055
HS-80C86RH
FIGURE 9. BUS TIMING - MAXIMUM MODE SYSTEM
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer ad-
dress is shown for the second INTA cycle.
5. Signals at HS-82C85RH or 82C88 are shown for reference only.
6. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T4.
Waveforms
(Continued)
T1
T2
T3
T4
TCLCL
TCH1CH2
TCL2CL1
TW
TCHCL
TCLCH
TCHSV
TCLSH
(SEE NOTE 8)
TCLDV
TCLAX
TCLAV
TCLAV
BHE, A19-A16
TSVLH
TCLLH
TR1VCL
TCHLL
TRYLCL
TCLR1X
TCLAV
TRYHCH
TDVCL
TCLDX1
TCLAX
AD15-AD0
DATA IN
TRYHSH
TCLRH
TRHAV
TCHDTL
TCLRL
TRLRH
TCHDTH
TAZRL
TCLML
TCLMH
TCVNV
TCVNX
TCLAZ
CLK
QS0, QS1
S2, S1, S0 (EXCEPT HALT)
BHE/S7, A19/S6-A16/S3
ALE (82C88 OUTPUT)
RDY
(HS-82C85RH INPUT)
NOTE 5
READY (HS-80C86RH INPUT)
READ CYCLE
82C88
OUTPUTS
SEE NOTES
5, 6
MRDC OR IORC
DEN
S7-S3
AD15-AD0
RD
DT/R
TCLAV
TCHRYX
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相關(guān)代理商/技術(shù)參數(shù) |
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| HS9-80C86RH/PROTO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| HS9-80C86RH-8 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 5MHZ 42CFPAK - Bulk |
| HS9-80C86RH-Q | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 5MHZ 42CFPAK - Bulk |
| HS9812R-PPM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PPM MULTIPLEX RECEIVER/DECODER |
| HS9-81C55RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 256 x 8 CMOS RAM |
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